文件名称:wyshizhong
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24 60 60时钟程序 用VHDL硬件编程语言实现的24进制60进制60进制时钟程序-24 60 60 clock procedures VHDL hardware programming language used to achieve the 24 M 60 M 60 M clock procedures
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下载文件列表
24.60.60时钟
............\1.txt
............\2.txt
............\clock2
............\......\automake.log
............\......\clock2.cmd_log
............\......\clock2.dhp
............\......\clock2.lso
............\......\clock2.ngc
............\......\clock2.ngr
............\......\clock2.npl
............\......\clock2.prj
............\......\clock2.stx
............\......\clock2.syr
............\......\clock2.vhdl
............\......\pepExtractor.prj
............\......\results.txt
............\......\test1.ado
............\......\test1.ANT
............\......\test1.tbw
............\......\test1.vhw
............\......\test2.ado
............\......\test2.ANT
............\......\test2.fdo
............\......\test2.tbw
............\......\test2.udo
............\......\test2.vhw
............\......\transcript
............\......\vsim.wlf
............\......\work
............\......\....\clock2
............\......\....\......\behavioral.asm
............\......\....\......\behavioral.dat
............\......\....\......\_primary.dat
............\......\....\clock2_cfg
............\......\....\..........\_primary.dat
............\......\....\..........\_vhdl.asm
............\......\....\test1
............\......\....\.....\testbench_arch.asm
............\......\....\.....\testbench_arch.dat
............\......\....\.....\_primary.dat
............\......\....\test2
............\......\....\.....\testbench_arch.asm
............\......\....\.....\testbench_arch.dat
............\......\....\.....\_primary.dat
............\......\....\_info
............\......\xst
............\......\...\work
............\......\...\....\hdllib.ref
............\......\...\....\hdpdeps.ref
............\......\...\....\sub00
............\......\...\....\.....\vhpl00.vho
............\......\...\....\.....\vhpl01.vho
............\......\__projnav
............\......\.........\clock2.gfl
............\......\.........\clock2.xst
............\......\.........\clock2_flowplus.gfl
............\......\.........\hb_cmds
............\......\.........\runXst_tcl.rsp
............\......\__projnav.log
............\wyclock
............\.......\automake.log
............\.......\clock.cmd_log
............\.......\clock.lso
............\.......\clock.ngc
............\.......\clock.ngr
............\.......\clock.prj
............\.......\clock.stx
............\.......\clock.syr
............\.......\clock.vhdl
............\.......\coregen.log
............\.......\coregen.prj
............\.......\pepExtractor.prj
............\.......\results.txt
............\.......\test.ado
............\.......\test.ANT
............\.......\test.fdo
............\.......\test.jhd
............\.......\test.tbw
............\.......\test.udo
............\.......\test.vhw
............\.......\test1.ado
............\.......\test1.ANT
............\.......\test1.fdo
............\.......\test1.tbw
............\.......\test1.udo
............\.......\test1.vhw
............\.......\test2.ado
............\.......\test2.ANT
............\.......\test2.tbw
............\.......\test2.vhw
............\.......\transcript
............\.......\vsim.wlf
............\.......\work
............\.......\....\clock
............\.......\....\.....\behavioral.asm
............\.......\....\.....\behavioral.dat
............\.......\....\.....\_primary.dat
............\.......\....\clock_cfg
............\.......\....\.........\_primary.dat
............\1.txt
............\2.txt
............\clock2
............\......\automake.log
............\......\clock2.cmd_log
............\......\clock2.dhp
............\......\clock2.lso
............\......\clock2.ngc
............\......\clock2.ngr
............\......\clock2.npl
............\......\clock2.prj
............\......\clock2.stx
............\......\clock2.syr
............\......\clock2.vhdl
............\......\pepExtractor.prj
............\......\results.txt
............\......\test1.ado
............\......\test1.ANT
............\......\test1.tbw
............\......\test1.vhw
............\......\test2.ado
............\......\test2.ANT
............\......\test2.fdo
............\......\test2.tbw
............\......\test2.udo
............\......\test2.vhw
............\......\transcript
............\......\vsim.wlf
............\......\work
............\......\....\clock2
............\......\....\......\behavioral.asm
............\......\....\......\behavioral.dat
............\......\....\......\_primary.dat
............\......\....\clock2_cfg
............\......\....\..........\_primary.dat
............\......\....\..........\_vhdl.asm
............\......\....\test1
............\......\....\.....\testbench_arch.asm
............\......\....\.....\testbench_arch.dat
............\......\....\.....\_primary.dat
............\......\....\test2
............\......\....\.....\testbench_arch.asm
............\......\....\.....\testbench_arch.dat
............\......\....\.....\_primary.dat
............\......\....\_info
............\......\xst
............\......\...\work
............\......\...\....\hdllib.ref
............\......\...\....\hdpdeps.ref
............\......\...\....\sub00
............\......\...\....\.....\vhpl00.vho
............\......\...\....\.....\vhpl01.vho
............\......\__projnav
............\......\.........\clock2.gfl
............\......\.........\clock2.xst
............\......\.........\clock2_flowplus.gfl
............\......\.........\hb_cmds
............\......\.........\runXst_tcl.rsp
............\......\__projnav.log
............\wyclock
............\.......\automake.log
............\.......\clock.cmd_log
............\.......\clock.lso
............\.......\clock.ngc
............\.......\clock.ngr
............\.......\clock.prj
............\.......\clock.stx
............\.......\clock.syr
............\.......\clock.vhdl
............\.......\coregen.log
............\.......\coregen.prj
............\.......\pepExtractor.prj
............\.......\results.txt
............\.......\test.ado
............\.......\test.ANT
............\.......\test.fdo
............\.......\test.jhd
............\.......\test.tbw
............\.......\test.udo
............\.......\test.vhw
............\.......\test1.ado
............\.......\test1.ANT
............\.......\test1.fdo
............\.......\test1.tbw
............\.......\test1.udo
............\.......\test1.vhw
............\.......\test2.ado
............\.......\test2.ANT
............\.......\test2.tbw
............\.......\test2.vhw
............\.......\transcript
............\.......\vsim.wlf
............\.......\work
............\.......\....\clock
............\.......\....\.....\behavioral.asm
............\.......\....\.....\behavioral.dat
............\.......\....\.....\_primary.dat
............\.......\....\clock_cfg
............\.......\....\.........\_primary.dat