文件名称:SerialPort
介绍说明－－下载内容均来自于网络，请自行研究使用
一个用verilog HDL 编写的串口发送程序，可以下载到FPGA中。已经在ActelFPGA中试过了，很好用。稍微修改之后，可以与Xilinx和Altera公司的FPGA兼容。-A programe dialogue to transmit a serial data which is writen by Verilog HDL.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
SerialPort
..........\component
..........\constraint
..........\coreconsole
..........\designer
..........\........\impl1
..........\........\.....\designer.log
..........\........\.....\designer_genhdl.log
..........\........\.....\simulation
..........\........\.....\transmit.adb
..........\........\.....\transmit.dtf
..........\........\.....\............\verify.log
..........\........\.....\transmit.ide_des
..........\........\.....\transmit.pdb
..........\........\.....\transmit.pdb.depends
..........\........\.....\transmit.tcl
..........\........\.....\transmit_fp
..........\........\.....\...........\$$FlashPro_FPBBALTLPT1.L$$
..........\........\.....\...........\projectData
..........\........\.....\...........\...........\transmit.pdb
..........\........\.....\...........\transmit.log
..........\........\.....\...........\transmit.pro
..........\hdl
..........\...\serialport.v
..........\...\serialport.v.bak
..........\...\waveperl.log
..........\phy_synthesis
..........\SerialPort.prj
..........\simulation
..........\..........\modelsim.ini
..........\..........\modelsim.ini.sav
..........\smartgen
..........\........\smartgen.aws
..........\stimulus
..........\synthesis
..........\.........\.recordref
..........\.........\backup
..........\.........\......\transmit.srr
..........\.........\coreip
..........\.........\run_options.txt
..........\.........\stdout.log
..........\.........\syntmp
..........\.........\......\transmit.msg
..........\.........\......\transmit.plg
..........\.........\transmit.areasrr
..........\.........\transmit.edn
..........\.........\transmit.map
..........\.........\transmit.sdf
..........\.........\transmit.so
..........\.........\transmit.srd
..........\.........\transmit.srm
..........\.........\transmit.srr
..........\.........\transmit.srs
..........\.........\transmit.tlg
..........\.........\transmit_drc.rpt
..........\.........\transmit_sdc.sdc
..........\.........\transmit_syn.prj
..........\.........\traplog.tlg
..........\transmit.pdb
..........\transmit.pdb.depends
..........\viewdraw
..........\........\sch
..........\........\sym
..........\........\vf
..........\........\..\project.lst
..........\........\viewdraw.ini
..........\........\wir
..........\单发程序.txt
..........\component
..........\constraint
..........\coreconsole
..........\designer
..........\........\impl1
..........\........\.....\designer.log
..........\........\.....\designer_genhdl.log
..........\........\.....\simulation
..........\........\.....\transmit.adb
..........\........\.....\transmit.dtf
..........\........\.....\............\verify.log
..........\........\.....\transmit.ide_des
..........\........\.....\transmit.pdb
..........\........\.....\transmit.pdb.depends
..........\........\.....\transmit.tcl
..........\........\.....\transmit_fp
..........\........\.....\...........\$$FlashPro_FPBBALTLPT1.L$$
..........\........\.....\...........\projectData
..........\........\.....\...........\...........\transmit.pdb
..........\........\.....\...........\transmit.log
..........\........\.....\...........\transmit.pro
..........\hdl
..........\...\serialport.v
..........\...\serialport.v.bak
..........\...\waveperl.log
..........\phy_synthesis
..........\SerialPort.prj
..........\simulation
..........\..........\modelsim.ini
..........\..........\modelsim.ini.sav
..........\smartgen
..........\........\smartgen.aws
..........\stimulus
..........\synthesis
..........\.........\.recordref
..........\.........\backup
..........\.........\......\transmit.srr
..........\.........\coreip
..........\.........\run_options.txt
..........\.........\stdout.log
..........\.........\syntmp
..........\.........\......\transmit.msg
..........\.........\......\transmit.plg
..........\.........\transmit.areasrr
..........\.........\transmit.edn
..........\.........\transmit.map
..........\.........\transmit.sdf
..........\.........\transmit.so
..........\.........\transmit.srd
..........\.........\transmit.srm
..........\.........\transmit.srr
..........\.........\transmit.srs
..........\.........\transmit.tlg
..........\.........\transmit_drc.rpt
..........\.........\transmit_sdc.sdc
..........\.........\transmit_syn.prj
..........\.........\traplog.tlg
..........\transmit.pdb
..........\transmit.pdb.depends
..........\viewdraw
..........\........\sch
..........\........\sym
..........\........\vf
..........\........\..\project.lst
..........\........\viewdraw.ini
..........\........\wir
..........\单发程序.txt