文件名称:clock
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FPGA的时钟算法 完整运行文件 通过Xilinx8.2的环境 波形仿真来实现时钟计数-FPGA clock algorithm to run it through a full environmental Xilinx8.2 simulation waveform to achieve the clock count
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下载文件列表
clock
.....\clock.asm.rpt
.....\clock.done
.....\clock.fit.eqn
.....\clock.fit.rpt
.....\clock.fit.summary
.....\clock.flow.rpt
.....\clock.map.eqn
.....\clock.map.rpt
.....\clock.map.summary
.....\clock.pin
.....\clock.pof
.....\clock.qpf
.....\clock.qsf
.....\clock.qws
.....\clock.sim.rpt
.....\clock.tan.rpt
.....\clock.tan.summary
.....\clock.vhd
.....\clock07022022.vwf
.....\db
.....\..\add_sub_onh.tdf
.....\..\add_sub_pnh.tdf
.....\..\clock.asm.qmsg
.....\..\clock.cbx.xml
.....\..\clock.cmp.cdb
.....\..\clock.cmp.hdb
.....\..\clock.cmp.qrpt
.....\..\clock.cmp.rdb
.....\..\clock.cmp.tdb
.....\..\clock.cmp0.ddb
.....\..\clock.dbp
.....\..\clock.db_info
.....\..\clock.eco.cdb
.....\..\clock.eds_overflow
.....\..\clock.fit.qmsg
.....\..\clock.fnsim.hdb
.....\..\clock.fnsim.qmsg
.....\..\clock.hier_info
.....\..\clock.hif
.....\..\clock.map.cdb
.....\..\clock.map.hdb
.....\..\clock.map.qmsg
.....\..\clock.pre_map.cdb
.....\..\clock.pre_map.hdb
.....\..\clock.psp
.....\..\clock.rtlv.hdb
.....\..\clock.rtlv_sg.cdb
.....\..\clock.rtlv_sg_swap.cdb
.....\..\clock.sgdiff.cdb
.....\..\clock.sgdiff.hdb
.....\..\clock.sim.hdb
.....\..\clock.sim.qmsg
.....\..\clock.sim.qrpt
.....\..\clock.sim.rdb
.....\..\clock.sim.vwf
.....\..\clock.sld_design_entry.sci
.....\..\clock.sld_design_entry_dsc.sci
.....\..\clock.syn_hier_info
.....\..\clock.tan.qmsg
.....\talkback
.....\........\clock.asm.talkback.xml
.....\........\clock.fit.talkback.xml
.....\........\clock.map.talkback.xml
.....\........\clock.sim.talkback.xml
.....\........\clock.tan.talkback.xml
.....\clock.asm.rpt
.....\clock.done
.....\clock.fit.eqn
.....\clock.fit.rpt
.....\clock.fit.summary
.....\clock.flow.rpt
.....\clock.map.eqn
.....\clock.map.rpt
.....\clock.map.summary
.....\clock.pin
.....\clock.pof
.....\clock.qpf
.....\clock.qsf
.....\clock.qws
.....\clock.sim.rpt
.....\clock.tan.rpt
.....\clock.tan.summary
.....\clock.vhd
.....\clock07022022.vwf
.....\db
.....\..\add_sub_onh.tdf
.....\..\add_sub_pnh.tdf
.....\..\clock.asm.qmsg
.....\..\clock.cbx.xml
.....\..\clock.cmp.cdb
.....\..\clock.cmp.hdb
.....\..\clock.cmp.qrpt
.....\..\clock.cmp.rdb
.....\..\clock.cmp.tdb
.....\..\clock.cmp0.ddb
.....\..\clock.dbp
.....\..\clock.db_info
.....\..\clock.eco.cdb
.....\..\clock.eds_overflow
.....\..\clock.fit.qmsg
.....\..\clock.fnsim.hdb
.....\..\clock.fnsim.qmsg
.....\..\clock.hier_info
.....\..\clock.hif
.....\..\clock.map.cdb
.....\..\clock.map.hdb
.....\..\clock.map.qmsg
.....\..\clock.pre_map.cdb
.....\..\clock.pre_map.hdb
.....\..\clock.psp
.....\..\clock.rtlv.hdb
.....\..\clock.rtlv_sg.cdb
.....\..\clock.rtlv_sg_swap.cdb
.....\..\clock.sgdiff.cdb
.....\..\clock.sgdiff.hdb
.....\..\clock.sim.hdb
.....\..\clock.sim.qmsg
.....\..\clock.sim.qrpt
.....\..\clock.sim.rdb
.....\..\clock.sim.vwf
.....\..\clock.sld_design_entry.sci
.....\..\clock.sld_design_entry_dsc.sci
.....\..\clock.syn_hier_info
.....\..\clock.tan.qmsg
.....\talkback
.....\........\clock.asm.talkback.xml
.....\........\clock.fit.talkback.xml
.....\........\clock.map.talkback.xml
.....\........\clock.sim.talkback.xml
.....\........\clock.tan.talkback.xml