文件名称:de2.1

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [MacOS] [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 7.39mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • z*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

这是一个基于FPGA/SOPC设计的简单串口程序,是FPGA硬件和niosII软件编程的结合。对初学者有很大的借鉴意义。在Quartus6.1和niosII6.1环境下编译通过,并且下载到板子上运行成功-This is based on FPGA/SOPC design a simple serial program is FPGA hardware and software combination niosII. Great for beginners reference. In Quartus6.1 and compiled through niosI6.1 environment and downloaded to the board to run a successful
相关搜索: 简单串口程序

(系统自动生成,下载前可以参看下载内容)

下载文件列表

de2.1

.....\cpu_0.v

.....\cpu_0_ic_tag_ram.mif

.....\cpu_0_jtag_debug_module.v

.....\cpu_0_jtag_debug_module_wrapper.v

.....\cpu_0_mult_cell.v

.....\cpu_0_ociram_default_contents.mif

.....\cpu_0_rf_ram_a.mif

.....\cpu_0_rf_ram_b.mif

.....\cpu_0_test_bench.v

.....\db

.....\..\altsyncram_4be1.tdf

.....\..\altsyncram_5be1.tdf

.....\..\altsyncram_c572.tdf

.....\..\altsyncram_cub1.tdf

.....\..\altsyncram_dtb1.tdf

.....\..\altsyncram_e502.tdf

.....\..\altsyncram_k1l1.tdf

.....\..\altsyncram_vke1.tdf

.....\..\decode_1oa.tdf

.....\..\decode_aoi.tdf

.....\..\ded_mult_2o81.tdf

.....\..\dffpipe_93c.tdf

.....\..\mult_add_4cr2.tdf

.....\..\mult_add_6cr2.tdf

.....\..\mux_ujb.tdf

.....\..\try.asm.qmsg

.....\..\try.asm_labs.ddb

.....\..\try.cbx.xml

.....\..\try.cmp.bpm

.....\..\try.cmp.cdb

.....\..\try.cmp.ecobp

.....\..\try.cmp.hdb

.....\..\try.cmp.logdb

.....\..\try.cmp.rdb

.....\..\try.cmp.tdb

.....\..\try.cmp0.ddb

.....\..\try.cmp_bb.cdb

.....\..\try.cmp_bb.hdb

.....\..\try.cmp_bb.logdb

.....\..\try.cmp_bb.rcf

.....\..\try.dbp

.....\..\try.db_info

.....\..\try.eco.cdb

.....\..\try.fit.qmsg

.....\..\try.hier_info

.....\..\try.hif

.....\..\try.map.bpm

.....\..\try.map.cdb

.....\..\try.map.ecobp

.....\..\try.map.hdb

.....\..\try.map.logdb

.....\..\try.map.qmsg

.....\..\try.map_bb.cdb

.....\..\try.map_bb.hdb

.....\..\try.map_bb.logdb

.....\..\try.merge.qmsg

.....\..\try.pre_map.cdb

.....\..\try.pre_map.hdb

.....\..\try.psp

.....\..\try.pss

.....\..\try.rtlv.hdb

.....\..\try.rtlv_sg.cdb

.....\..\try.rtlv_sg_swap.cdb

.....\..\try.sgdiff.cdb

.....\..\try.sgdiff.hdb

.....\..\try.signalprobe.cdb

.....\..\try.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.atm

.....\..\try.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.logdb

.....\..\try.sld_design_entry.sci

.....\..\try.sld_design_entry_dsc.sci

.....\..\try.smp_dump.txt

.....\..\try.syn_hier_info

.....\..\try.tan.qmsg

.....\nios_system.bsf

.....\nios_system.ptf

.....\nios_system.v

.....\nios_system_generation_script

.....\nios_system_log.txt

.....\nios_system_setup_quartus.tcl

.....\nios_system_sim

.....\...............\cpu_0_ic_tag_ram.dat

.....\...............\cpu_0_ic_tag_ram.hex

.....\...............\cpu_0_ociram_default_contents.dat

.....\...............\cpu_0_ociram_default_contents.hex

.....\...............\cpu_0_rf_ram_a.dat

.....\...............\cpu_0_rf_ram_a.hex

.....\...............\cpu_0_rf_ram_b.dat

.....\...............\cpu_0_rf_ram_b.hex

.....\...............\create_nios_system_project.do

.....\...............\list_presets.do

.....\...............\modelsim.tcl

.....\...............\onchip_memory_0.dat

.....\...............\onchip_memory_0.sym

.....\...............\setup_sim.do

.....\...............\uart_0_input_data_mutex.dat

.....\...............\uart_0_input_data_stream.dat

.....\...............\uart_0_log_module.txt

.....\...............\virtuals.do

.....\...............\wave_presets.do

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