文件名称:dct2
介绍说明－－下载内容均来自于网络，请自行研究使用
这个是一个基于FPGA的数字图像的整数DCT变换程序，程序高性能地实现了2维DCT变换。-This is an FPGA-based digital image of the integer DCT transform process and procedures to achieve high-performance 2-D DCT transform.
相关搜索： integer
transform
dct
Integer
DCT
dct
2D
fpga
2d
dct
dct2
dct
fpga
2D
dct
fpga
INTEGER
dct
TRANSFORM
dct
2d
vhdl
transform
dct
Integer
DCT
dct
2D
fpga
2d
dct
dct2
dct
fpga
2D
dct
fpga
INTEGER
dct
TRANSFORM
dct
2d
vhdl
(系统自动生成,下载前可以参看下载内容)
下载文件列表
实战训练21 整数DCT变换的设计与实现
..................................\1ddct
..................................\.....\.untf
..................................\.....\1ddct.dhp
..................................\.....\1ddct.ise
..................................\.....\1ddct.ise_ISE_Backup
..................................\.....\automake.log
..................................\.....\d1_dct.v
..................................\.....\dct.bld
..................................\.....\dct.cmd_log
..................................\.....\dct.lso
..................................\.....\dct.mrp
..................................\.....\dct.nc1
..................................\.....\dct.ncd
..................................\.....\dct.ngc
..................................\.....\dct.ngd
..................................\.....\dct.ngm
..................................\.....\dct.ngr
..................................\.....\dct.pad
..................................\.....\dct.pad_txt
..................................\.....\dct.par
..................................\.....\dct.par_nlf
..................................\.....\dct.pcf
..................................\.....\dct.placed_ncd_tracker
..................................\.....\dct.prj
..................................\.....\dct.routed_ncd_tracker
..................................\.....\dct.stx
..................................\.....\dct.syr
..................................\.....\dct.twr
..................................\.....\dct.twx
..................................\.....\dct.versim_par
..................................\.....\dct.xpi
..................................\.....\dct_map.ncd
..................................\.....\dct_map.ngm
..................................\.....\dct_pad.csv
..................................\.....\dct_pad.txt
..................................\.....\dct_summary.html
..................................\.....\dct_test.cmd_log
..................................\.....\dct_test.lso
..................................\.....\dct_test.prj
..................................\.....\dct_test.syr
..................................\.....\dct_test_summary.html
..................................\.....\dct_test_vhdl.prj
..................................\.....\dct_timesim.nlf
..................................\.....\dct_timesim.sdf
..................................\.....\dct_timesim.v
..................................\.....\dct_vhdl.prj
..................................\.....\idtest.ant
..................................\.....\idtest.fdo
..................................\.....\idtest.jhd
..................................\.....\idtest.tbw
..................................\.....\idtest.tdo
..................................\.....\idtest.tfw
..................................\.....\idtest.timesim_tfw
..................................\.....\idtest.udo
..................................\.....\idtest.xwv
..................................\.....\idtest.xwv_bak
..................................\.....\idtest_bencher.prj
..................................\.....\Project.dhp
..................................\.....\results.txt
..................................\.....\transcript
..................................\.....\vsim.wlf
..................................\.....\work
..................................\.....\....\dct
..................................\.....\....\...\verilog.asm
..................................\.....\....\...\_primary.dat
..................................\.....\....\...\_primary.vhd
..................................\.....\....\glbl
..................................\.....\....\....\verilog.asm
..................................\.....\....\....\_primary.dat
..................................\.....\....\....\_primary.vhd
..................................\.....\....\idtest
..................................\.....\....\......\verilog.asm
..................................\.....\....\......\_primary.dat
..................................\.....\....\......\_primary.vhd
..................................\.....\....\_info
.................
..................................\1ddct
..................................\.....\.untf
..................................\.....\1ddct.dhp
..................................\.....\1ddct.ise
..................................\.....\1ddct.ise_ISE_Backup
..................................\.....\automake.log
..................................\.....\d1_dct.v
..................................\.....\dct.bld
..................................\.....\dct.cmd_log
..................................\.....\dct.lso
..................................\.....\dct.mrp
..................................\.....\dct.nc1
..................................\.....\dct.ncd
..................................\.....\dct.ngc
..................................\.....\dct.ngd
..................................\.....\dct.ngm
..................................\.....\dct.ngr
..................................\.....\dct.pad
..................................\.....\dct.pad_txt
..................................\.....\dct.par
..................................\.....\dct.par_nlf
..................................\.....\dct.pcf
..................................\.....\dct.placed_ncd_tracker
..................................\.....\dct.prj
..................................\.....\dct.routed_ncd_tracker
..................................\.....\dct.stx
..................................\.....\dct.syr
..................................\.....\dct.twr
..................................\.....\dct.twx
..................................\.....\dct.versim_par
..................................\.....\dct.xpi
..................................\.....\dct_map.ncd
..................................\.....\dct_map.ngm
..................................\.....\dct_pad.csv
..................................\.....\dct_pad.txt
..................................\.....\dct_summary.html
..................................\.....\dct_test.cmd_log
..................................\.....\dct_test.lso
..................................\.....\dct_test.prj
..................................\.....\dct_test.syr
..................................\.....\dct_test_summary.html
..................................\.....\dct_test_vhdl.prj
..................................\.....\dct_timesim.nlf
..................................\.....\dct_timesim.sdf
..................................\.....\dct_timesim.v
..................................\.....\dct_vhdl.prj
..................................\.....\idtest.ant
..................................\.....\idtest.fdo
..................................\.....\idtest.jhd
..................................\.....\idtest.tbw
..................................\.....\idtest.tdo
..................................\.....\idtest.tfw
..................................\.....\idtest.timesim_tfw
..................................\.....\idtest.udo
..................................\.....\idtest.xwv
..................................\.....\idtest.xwv_bak
..................................\.....\idtest_bencher.prj
..................................\.....\Project.dhp
..................................\.....\results.txt
..................................\.....\transcript
..................................\.....\vsim.wlf
..................................\.....\work
..................................\.....\....\dct
..................................\.....\....\...\verilog.asm
..................................\.....\....\...\_primary.dat
..................................\.....\....\...\_primary.vhd
..................................\.....\....\glbl
..................................\.....\....\....\verilog.asm
..................................\.....\....\....\_primary.dat
..................................\.....\....\....\_primary.vhd
..................................\.....\....\idtest
..................................\.....\....\......\verilog.asm
..................................\.....\....\......\_primary.dat
..................................\.....\....\......\_primary.vhd
..................................\.....\....\_info
.................