文件名称:OpenRisc

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 765kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 邓**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

开源软核处理器OpenRisc的SOPC设计
相关搜索: openrisc
软核
OPENRISC
RAR

(系统自动生成,下载前可以参看下载内容)

下载文件列表

or1200-1.35

...........\bench

...........\.....\verilog

...........\.....\.......\or1200_top_bench.v

...........\.....\.......\timescale.v

...........\rtl

...........\...\verilog

...........\...\.......\or1200_alu.v

...........\...\.......\or1200_amultp2_32x32.v

...........\...\.......\or1200_cfgr.v

...........\...\.......\or1200_cpu.v

...........\...\.......\or1200_ctrl.v

...........\...\.......\or1200_dc_fsm.v

...........\...\.......\or1200_dc_ram.v

...........\...\.......\or1200_dc_tag.v

...........\...\.......\or1200_dc_top.v

...........\...\.......\or1200_defines.v

...........\...\.......\or1200_dmmu_tlb.v

...........\...\.......\or1200_dmmu_top.v

...........\...\.......\or1200_dpram_32x32.v

...........\...\.......\or1200_du.v

...........\...\.......\or1200_except.v

...........\...\.......\or1200_freeze.v

...........\...\.......\or1200_genpc.v

...........\...\.......\or1200_gmultp2_32x32.v

...........\...\.......\or1200_ic_fsm.v

...........\...\.......\or1200_ic_ram.v

...........\...\.......\or1200_ic_tag.v

...........\...\.......\or1200_ic_top.v

...........\...\.......\or1200_if.v

...........\...\.......\or1200_immu_tlb.v

...........\...\.......\or1200_immu_top.v

...........\...\.......\or1200_lsu.v

...........\...\.......\or1200_mem2reg.v

...........\...\.......\or1200_mult_mac.v

...........\...\.......\or1200_operandmuxes.v

...........\...\.......\or1200_pic.v

...........\...\.......\or1200_pm.v

...........\...\.......\or1200_reg2mem.v

...........\...\.......\or1200_rf.v

...........\...\.......\or1200_rfram_generic.v

...........\...\.......\or1200_sb.v

...........\...\.......\or1200_sb_fifo.v

...........\...\.......\or1200_spram_1024x32.v

...........\...\.......\or1200_spram_1024x8.v

...........\...\.......\or1200_spram_2048x32.v

...........\...\.......\or1200_spram_2048x8.v

...........\...\.......\or1200_spram_256x21.v

...........\...\.......\or1200_spram_512x20.v

...........\...\.......\or1200_spram_64x14.v

...........\...\.......\or1200_spram_64x22.v

...........\...\.......\or1200_spram_64x24.v

...........\...\.......\or1200_sprs.v

...........\...\.......\or1200_top.v

...........\...\.......\or1200_tpram_32x32.v

...........\...\.......\or1200_tt.v

...........\...\.......\or1200_wbmux.v

...........\...\.......\or1200_wb_biu.v

...........\...\.......\or1200_xcv_ram32x8d.v

...........\...\.......\timescale.v

...........\sim

...........\...\rtl_sim

...........\...\.......\modelsim_sim

...........\...\.......\............\modelsim.ini

...........\...\.......\............\or1200.cr.mti

...........\...\.......\............\or1200.mpf

...........\...\.......\............\run.do

...........\...\.......\............\transcript

...........\...\.......\............\vlog.opt

...........\...\.......\............\vsim.wlf

...........\...\.......\............\wave.do

...........\...\.......\............\work

...........\...\.......\............\....\or1200_alu

...........\...\.......\............\....\..........\verilog.asm

...........\...\.......\............\....\..........\_primary.dat

...........\...\.......\............\....\..........\_primary.vhd

...........\...\.......\............\....\or1200_cfgr

...........\...\.......\............\....\...........\verilog.asm

...........\...\.......\............\....\...........\_primary.dat

...........\...\.......\............\....\...........\_primary.vhd

...........\...\.......\............\....\or1200_cpu

...........\...\.......\............\....\..........\verilog.asm

...........\...\.......\............\....\..........\_primary.dat

...........\...\.......\............\....\..........\_primary.vhd

...........\...\.......\............\....\or1200_ctrl

...........\...\.......\............\....\...........\verilog.asm

...........\...\.......\............\....\...........\_primary.dat

...........\...\.......\............\....\...........\_primary.vhd

...........\...\.......\............\....\or1200_dc_fsm

...........\...\.......\............\....\.............\verilog.asm

...........\...\.......\............\....\.............\_primary.dat

...........\...\.......\............\...

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