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文件名称:uart8

  • 所属分类：
  • VHDL编程
  • 资源属性：
  • [VHDL] [源码]
  • 上传时间：
  • 2012-11-26
  • 文件大小：
  • 856kb
  • 下载次数：
  • 0次
  • 提 供 者：
  • 张*
  • 相关连接：
  • 无
  • 下载说明：
  • 别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容均来自于网络，请自行研究使用

使用Libero提供的异步通信IP核实现UART通信，并附带仿真程序。UART设置为1位开始位，8位数据位，1位停止位，无校验。且UART发送自带2级FIFO缓冲，占用FPGA面积很小。-Libero provided the use of asynchronous communication IP core implementation UART communications, and incidental simulation program. UART is set to 1 to start bit, 8 data bits, 1 stop bit, no parity. UART and send its own two FIFO buffer occupancy is very small FPGA.
相关搜索： UART
IMplementation
in
FPGA
uart
vhdl
asynchronous
buffer
in
vhdl
UART
VHDL
UART
IP
libero8
5
uart
ip
uart8
ip
core
communication
vhdl

(系统自动生成,下载前可以参看下载内容)

下载文件列表

uart8

.....\component

.....\.........\Actel

.....\.........\.....\DirectCore

.....\.........\.....\..........\COREUART

.....\.........\.....\..........\........\3.1.103

.....\.........\.....\..........\........\.......\coreparameters.v

.....\.........\.....\..........\........\.......\COREUART.cxf

.....\.........\.....\..........\........\.......\mti

.....\.........\.....\..........\........\.......\...\lib_vlog_obs

.....\.........\.....\..........\........\.......\...\............\COREUART_LIB

.....\.........\.....\..........\........\.......\...\............\............\_info

.....\.........\.....\..........\........\.......\...\scripts

.....\.........\.....\..........\........\.......\...\.......\wave_vlog.do

.....\.........\.....\..........\........\.......\rtl

.....\.........\.....\..........\........\.......\...\vlog

.....\.........\.....\..........\........\.......\...\....\core_obfuscated

.....\.........\.....\..........\........\.......\...\....\...............\Clock_gen.v

.....\.........\.....\..........\........\.......\...\....\...............\CoreUART.v

.....\.........\.....\..........\........\.......\...\....\...............\fifo_256x8_pa3.v

.....\.........\.....\..........\........\.......\...\....\...............\Rx_async.v

.....\.........\.....\..........\........\.......\...\....\...............\Tx_async.v

.....\.........\.....\..........\........\.......\...\....\test

.....\.........\.....\..........\........\.......\...\....\....\verif

.....\.........\.....\..........\........\.......\...\....\....\.....\testbnch.v

.....\.........\work

.....\.........\....\UartIP

.....\.........\....\......\testbench.v

.....\.........\....\......\UartIP.cxf

.....\.........\....\......\UartIP.sdb

.....\.........\....\......\UartIP.v

.....\constraint

.....\..........\uart_ctrl.sdc

.....\coreconsole

.....\...........\UartIP

.....\designer

.....\........\impl1

.....\........\.....\designer.log

.....\........\.....\designer_genhdl.log

.....\........\.....\PLL_1536.ide_des

.....\........\.....\PLL_33.ide_des

.....\........\.....\simulation

.....\........\.....\UartIP.ide_des

.....\........\.....\uart_control.ide_des

.....\........\.....\uart_ctrl.adb

.....\........\.....\uart_ctrl.dtf

.....\........\.....\.............\verify.log

.....\........\.....\uart_ctrl.ide_des

.....\........\.....\uart_ctrl.pdb

.....\........\.....\uart_ctrl.pdb.depends

.....\........\.....\uart_ctrl.stp

.....\........\.....\uart_ctrl.tcl

.....\........\.....\uart_ctrl_fp

.....\........\.....\............\$$FlashPro_08166.L$$

.....\........\.....\............\$$FlashPro_08424.L$$

.....\........\.....\............\projectData

.....\........\.....\............\...........\uart_ctrl.pdb

.....\........\.....\............\uart_ctrl.log

.....\........\.....\............\uart_ctrl.pro

.....\........\.....\uart_initial.ide_des

.....\hdl

.....\...\interface.v

.....\...\uart_control.v~RF14e5b17.TMP

.....\...\uart_control.v~RF1a74220.TMP

.....\...\uart_control.v~RF58c8e1.TMP

.....\...\uart_ctrl.v

.....\...\uart_ctrl.v.bak

.....\...\uart_ctrl.v~RF105819e.TMP

.....\...\uart_ctrl.v~RF17d802f.TMP

.....\...\uart_ctrl.v~RF1ec6b34.TMP

.....\...\uart_ctrl.v~RF275e2bb.TMP

.....\...\uart_initial.v

.....\...\uart_initial.v~RF1057e04.TMP

.....\phy_synthesis

.....\simulation

.....\..........\modelsim.ini

.....\..........\modelsim.ini.sav

.....\..........\modelsim.log

.....\..........\postsynth

.....\..........\.........\@c@o@r@e@u@a@r@t_0s_0s_15s

.....\..........\.........\..........................\verilog.psm

.....\..........\.........\..........................\_primary.dat

.....\..........\.........\..........................\_primary.dbs

.....\..........\.........\..........................\_primary.vhd

.....\..........\.........\@clock_gen

.....\..........\.........\..........\verilog.psm

.....\..........\.........\..........\_primary.dat

.....\..........\.........\..........\_primary.dbs

.....\..........\.........\..........\_primary.vhd

.....\..........\.........\@p@l@l_33

.....\..........\.........\.........\verilog.psm

.....\..........\.........\.........\_prim

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