[VHDL编程] ADC0809

说明：用状态机对A/D转换器0809的采样控制电路的实现。工具：Quartus ii 6.0 语言：VHDL-State machine used for A/D converter sampling control circuit 0809 is achieved. Tools: Quartus ii 6.0 Language: VHDL
<杨晴飞> 在 2024-11-19 上传 | 大小：45kb | 下载：0

[VHDL编程] myled4

说明：四位动态数码管显示数字时钟的分位和秒位。工具：Quartus ii 6.0 语言：VHDL-4 shows the number of dynamic digital tube digital clock and seconds bit. Tools: Quartus ii 6.0 Language: VHDL
<杨晴飞> 在 2024-11-19 上传 | 大小：187kb | 下载：0

[VHDL编程] myf_adder

说明：用例化语句和case语句编写的全加器的VHDL描述。-Of statements were prepared using the full adder of the VHDL descr iption.
<杨晴飞> 在 2024-11-19 上传 | 大小：63kb | 下载：0

[VHDL编程] myclk

说明：两位独立数码管100进制计数器，每1秒计数一次。从0到99，到99后又回到0.-Two independent 100-band digital tube counters, every time 1 seconds count. From 0 to 99, to 99 and then back to 0.
<杨晴飞> 在 2024-11-19 上传 | 大小：165kb | 下载：0

[VHDL编程] myled

说明：利用if语句实现流水灯设计。工具：Quartus ii 6.0 语言：VHDL-If statement using lights to achieve the design flow. Tools: Quartus ii 6.0 Language: VHDL
<杨晴飞> 在 2024-11-19 上传 | 大小：103kb | 下载：0

[VHDL编程] tut_DE2_sdram_vhdl

说明：This tutorial explains how the SDRAM chip on ltera’s DE2 Development and Education board can be used with a Nios II system implemented by using the Altera SOPC Builder.
<*Roma*> 在 2024-11-19 上传 | 大小：534kb | 下载：0

[VHDL编程] tut_debug_software_verilogDE2

说明：This tutorial presents some basic concepts that can be helpful in debugging of application programs written in the Nios II assembly language, which run on Altera’s DE2 boards.
<*Roma*> 在 2024-11-19 上传 | 大小：135kb | 下载：0

[VHDL编程] tut_nios2_introduction

说明：This tutorial presents an introduction to Altera’s Nios R II processor, which is a soft processor that can be in- stantiated on an Altera FPGA device. It describes the basic architecture of Nios II and its instructi
<*Roma*> 在 2024-11-19 上传 | 大小：114kb | 下载：0

[VHDL编程] tut_embedded_programming_verilog_C_DE2

说明：This tutorial explains how to communicate with IO devices on the DE2 Board and how to deal with interrupts using C and the Altera Monitor Program. Two example programs are given that diplay the state of the toggle switch
<*Roma*> 在 2024-11-19 上传 | 大小：163kb | 下载：0

[VHDL编程] edh_ed_handbook

说明：Altera® provides various tools for development of hardware and software for embedded systems. This handbook complements the primary documentation for these tools by describing how to most effectively use the tools. I
<*Roma*> 在 2024-11-19 上传 | 大小：1.83mb | 下载：0

[VHDL编程] crc

说明：VHDL cyclic redundancy check generator und receiver
<Digitalkurt> 在 2024-11-19 上传 | 大小：4kb | 下载：0

[VHDL编程] Center

说明：使用Xilinx3S400开发的钢板检测算法中心化算法，通过测试。-a vhdl-program use Xilinx3S400
<刘朝朋> 在 2024-11-19 上传 | 大小：849kb | 下载：0