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[VHDL编程] DATA_scramble
说明:扰码器的verilog实现,参考802.11a相关标准-Scrambler in verilog implementation<> 在 2025-04-24 上传 | 大小:1kb | 下载:0
[VHDL编程] paomadenghe60jinzhi
说明:一个用VHDL编写的跑马灯程序和60进制计数器的程序,一个是自己设计的一个是老师要求,都在实验箱上验证成功,希望对大家有所帮助。-Marquee with a program written in VHDL, and 60 binary counter program, one designed by one teacher asked, are in the experimental boxes proved to be succes<zhangliang> 在 2025-04-24 上传 | 大小:251kb | 下载:0
[VHDL编程] DividerVHDL
说明:使用VHDL进行分频器设计,主要是一些分频的东西,整数分频,小数分频,奇次分频和偶次分频-Divider using VHDL to design, mainly because some sub-band stuff, integer divider, fractional-N, odd and even sub-sub-sub-sub-band frequency<赵勇涛> 在 2025-04-24 上传 | 大小:315kb | 下载:0
[VHDL编程] bcdtoexcess3
说明:this the program which can help to convert bcd code to excess3 code,the perfect circuitary has been given in this document which will lead you to understand it more properly.Reference is taken from morris mano book of di<jatab> 在 2025-04-24 上传 | 大小:276kb | 下载:0