[VHDL编程] 05-NEC_2003_D

说明：简易逻辑分析仪（2003年D题），verilog源程序-Simple logic analyzer (, 2003 D), Verilog source code
<艾米丽> 在 2025-03-06 上传 | 大小：408kb | 下载：0

[VHDL编程] 06-NEC_2005_A

说明：06-正弦信号发生器（2005年A题），verilog源程序-06- sinusoidal signal generator (2005 A question), Verilog source code
<艾米丽> 在 2025-03-06 上传 | 大小：707kb | 下载：0

[VHDL编程] alarm

说明：The red arrow showed the output became 8 when the measured temperature changed to 11°C. As shown by black arrow, the maximum output was 28. The program was run according to the proposed method.
<jayjay> 在 2025-03-06 上传 | 大小：99kb | 下载：0

[VHDL编程] comp

说明：The red arrow showed the output became 8 when the measured temperature changed to 11°C. As shown by black arrow, the maximum output was 28. The program was run according to the proposed method.
<jayjay> 在 2025-03-06 上传 | 大小：112kb | 下载：0

[VHDL编程] 8.3-LCD

说明：FPGA驱动LCD显示中文字符程序及状态机的使用-FPGA to drive the LCD display Chinese characters procedures and the use of the state machine
<林高办> 在 2025-03-06 上传 | 大小：5kb | 下载：0

[VHDL编程] curtain

说明：The red arrow showed the output became 8 when the measured temperature changed to 11°C. As shown by black arrow, the maximum output was 28. The program was run according to the proposed method.
<jayjay> 在 2025-03-06 上传 | 大小：112kb | 下载：0

[VHDL编程] lighting

说明：The red arrow showed the output became 8 when the measured temperature changed to 11°C. As shown by black arrow, the maximum output was 28. The program was run according to the proposed method.
<jayjay> 在 2025-03-06 上传 | 大小：89kb | 下载：0

[VHDL编程] modulated_gen

说明：The red arrow showed the output became 8 when the measured temperature changed to 11°C. As shown by black arrow, the maximum output was 28. The program was run according to the proposed method.
<jayjay> 在 2025-03-06 上传 | 大小：183kb | 下载：0

[VHDL编程] RD1055_rev01.3

说明： NAND Flash Controller Reference Design RD10- NAND Flash Controller Reference Design RD1055
<akjfklaskdfj> 在 2025-03-06 上传 | 大小：584kb | 下载：0

[VHDL编程] NAND_Flash_Interface_DF

说明：actel NAND Flash Interface Design Example
<akjfklaskdfj> 在 2025-03-06 上传 | 大小：2.48mb | 下载：0

[VHDL编程] sata_controller_core_latest.tar

说明：The SATA2 core implements the Command, Transport and Link Layers of the SATA2 protocol and provides a Physical Layer Wrapper for the transceivers.
<akjfklaskdfj> 在 2025-03-06 上传 | 大小：53kb | 下载：0

[VHDL编程] 4613m73a_nand_model

说明：File Descr iptions: --- --- --- nand_model.v -structural wrapper for nand_die_model nand_die_model.v -nand model of a single die nand_defines.vh -file used to generate correct port maps for nand_model instanciat
<akjfklaskdfj> 在 2025-03-06 上传 | 大小：86kb | 下载：0