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[VHDL编程round_robin

说明:Round Robin priority arbiter
<taso999 > 在 2024-11-14 上传 | 大小:46kb | 下载:0

[VHDL编程IP核的生成

说明:讲述了FPGA中IP核的使用方法,对于初学者很有帮助。(The method of using IP core in FPGA is described.)
<jihan > 在 2024-11-14 上传 | 大小:2.94mb | 下载:0

[VHDL编程SPI_controller

说明:SPI controller (fpga/verilog)
<taso999 > 在 2024-11-14 上传 | 大小:117kb | 下载:0

[VHDL编程基于IP核的ISE设计流程

说明:讲述了在ISE中如何通过建立ip核,使用ip核可以增加程序设计的效率。(In ISE, how to use the IP core can increase the efficiency of the program design by establishing the IP core.)
<jihan > 在 2024-11-14 上传 | 大小:2.38mb | 下载:0

[VHDL编程spi master slave

说明:SPI master slave (fpga/verilog)
<taso999 > 在 2024-11-14 上传 | 大小:66kb | 下载:0

[VHDL编程Coding Files

说明:Through this paper our attempt is to give a onetime networking solution by the means of merging the VLSI field with the networking field as now a days the router is the key player in networking domain so the focus remain
<kutti > 在 2024-11-14 上传 | 大小:12kb | 下载:0

[VHDL编程Coding files

说明:The past several years have witnessed a rapid development in the wireless network area. So far wireless networking has been focused on high speed and long range applications. Zigbee technology was developed for a Wireles
<kutti > 在 2024-11-14 上传 | 大小:8kb | 下载:0

[VHDL编程Coding Files

说明:We present an efficient hardware architecture design & implementation of Advanced Encryption Standard AES Rijndael cryptosystem. The AES algorithm defined by the National Institute of Standard and Technology NIST of
<kutti > 在 2024-11-14 上传 | 大小:27kb | 下载:0

[VHDL编程Coding Files

说明:Floating Point FP multiplication is widely used in large set of scientific and signal processing computation. Multiplication is one of the common arithmetic operations in these computations. A high sp
<kutti > 在 2024-11-14 上传 | 大小:51kb | 下载:0

[VHDL编程wangfei

说明:基于FPGA的一个LCD显示的网费计价系统设计(costing system of network)
<月月1234 > 在 2024-11-14 上传 | 大小:3kb | 下载:0

[VHDL编程slave_control

说明:VHDL实现spi,从机实现方法,实现32个bit传输,单向传输。(VHDL implementation of SPI, from the machine implementation method, the realization of 32 bit transmission, one-way transmission.)
<许大牛 > 在 2024-11-14 上传 | 大小:1kb | 下载:0

[VHDL编程Verilog_1Gb_DDR3_G_Die

说明:ddr3控制器,速率可达1Gbps,语言使用verilog,已经加入tb(ddr3 controller, can be used to ddr3 control,high speed)
<aikannba > 在 2024-11-14 上传 | 大小:33kb | 下载:0
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