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[VHDL编程11FIRfliter

说明:11阶FIR滤波器和(7,4)编码器的Verilog语言,高手的作品,放心下-11-order FIR filter, and (7,4) encoder of the Verilog language, master' s works, rest assured that the next
<王刚> 在 2025-01-25 上传 | 大小:2kb | 下载:0

[VHDL编程delay

说明:一个可以把信号拉长任意个CLk的VHDL源码例子。详见说明文档-A signal can be stretched any one CLk the VHDL source code examples. See documentation
<tofly> 在 2025-01-25 上传 | 大小:2kb | 下载:0

[VHDL编程vhdlclock

说明:making a simple clock using altera vhdl
<mantisar> 在 2025-01-25 上传 | 大小:2kb | 下载:0

[VHDL编程qiangdaqi

说明:四人抢答器,已通过编译,仿真,包括抢答识别、计分、计时、数字显示等功能。-Four Responder, has passed the compilation, simulation, including the answer in his identification, scoring, timing and digital display.
<majianhui> 在 2025-01-25 上传 | 大小:2kb | 下载:0

[VHDL编程spi_eeprom_conf

说明:实现spi接口的传输,并多外接EEPROM读写数据-Spi interface to achieve the transfer, and multiple external EEPROM read and write data
<guoguo> 在 2025-01-25 上传 | 大小:2kb | 下载:0

[VHDL编程spi_master_phy

说明:这是spi接口传输的一部分内容,本源码一共三部分,功能:spi接口的的实现即对外设的读写数据-This is the spi interface transfer part of the contents of a total of three parts of this source, function: spi interface that the realization of the read and write data to
<guoguo> 在 2025-01-25 上传 | 大小:2kb | 下载:0

[VHDL编程clock2Hz

说明:this fpga spartan 3e based project file .the project is the game based on vga. this file contains 2,20,25,400Hz clock generating file as per required for the project.-this is fpga spartan 3e based project file .the pro
<yasir > 在 2025-01-25 上传 | 大小:2kb | 下载:0

[VHDL编程game

说明:this a fpga sparttan 3e based project in which i have made a game based on vga interface . this file is the main file included in the project.-this is a fpga sparttan 3e based project in which i have made a game
<yasir > 在 2025-01-25 上传 | 大小:2kb | 下载:0

[VHDL编程keyb

说明:this a fpga sparttan 3e based project in which i have made a game based on vga interface . this file is the supporting file for keyboard interface and it also included a intro.vhdl file required for the startup anim
<yasir > 在 2025-01-25 上传 | 大小:2kb | 下载:0

[VHDL编程hello_world

说明:欢迎大家使用该程序,是在FPGA下使用开发的。请大家使用。-Welcome to use the program is to use FPGA development. Please use the.
<刘金才> 在 2025-01-25 上传 | 大小:2kb | 下载:0

[VHDL编程count

说明:用VHDL编写的4、7、40、64、84计数器,可将程序中的具体数字设成任意值。-Using VHDL written 4,7,40,64,84 counter, you can program specific figures set to any value.
<cloudy> 在 2025-01-25 上传 | 大小:2kb | 下载:0

[VHDL编程FFT

说明:FPGA嵌入式 fft 用FPGA实现FFT算法-FPGA fft
<asd> 在 2025-01-25 上传 | 大小:2kb | 下载:0
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