资源列表
[VHDL编程] convolution
说明:This the code for the convolutional and the test bench for this in the verilog code.-This is the code for the convolutional and the test bench for this in the verilog code.<rion> 在 2024-10-12 上传 | 大小:1024 | 下载:0
[VHDL编程] demapperSharp1(16QAM)
说明:This the code for the demapper in the verilog code.-This is the code for the demapper in the verilog code.<rion> 在 2024-10-12 上传 | 大小:1024 | 下载:0
[VHDL编程] inter_deleaver
说明:This the code for the interleaver and the deinterleaver in the verilog code.-This is the code for the interleaver and the deinterleaver in the verilog code.<rion> 在 2024-10-12 上传 | 大小:2048 | 下载:0
[VHDL编程] mapperSharp1(16QAM)
说明:This the code for the mapper in the verilog code.-This is the code for the mapper in the verilog code.<rion> 在 2024-10-12 上传 | 大小:1024 | 下载:0
[VHDL编程] mt9d112_ddr2
说明:镁光MT9基于FPGA图像采集模块,该模块可同时采集两路视频信号。其包括完整的时序和接口、ddr2内存数据写入和存储、qsys系统的搭建、FPGA与NIOS II联合设计-Micron MT9 based on FPGA image acquisition module, the module can simultaneously capture two video signals. Including the complete tim<豪> 在 2024-10-12 上传 | 大小:39202816 | 下载:0
[VHDL编程] RD1213_Video_Pipeline
说明:This document describes the structure and implementation of a video pipeline demo design running in the Lattice ECP3-150EA-8FN1156C device based on the Sparrowhawk FX Board. This demo takes two of the four video stre<吴> 在 2024-10-12 上传 | 大小:6755328 | 下载:0
[VHDL编程] FIFOonFPGAtoUSB
说明:这个一个基于FPGA的FIFO的传输资料,可以用在USB的传输上,里面有视频有源代码,还有估计的设计,相关的文档说明等等。-The transmission of a data FIFO of FPGA-based, can be used on USB transmission, which has a video source code, as well as estimates of design, related documen<jav> 在 2024-10-12 上传 | 大小:12653568 | 下载:0