说明:QPSK调制程序的testbench程序
timescale 1ns/1ns //单位时间,时间精度
module qpsk_tb //qpsk调制的testbench
reg clk
reg rst
reg x
wire y
-QPSK modulation program testbench program timescale 1ns/1ns // unit of time, time a <soulwyc> 在 2024-11-16 上传
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说明:LTE通信中DCT算法的VERILOG实现,给初学者提供参考。-LTE communication VERILOG algorithm DCT implementation, to provide a reference for beginners. <kobe> 在 2024-11-16 上传
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说明:LTE通信中的cfft算法的VERILOG实现,具有一定的参考意义。-LTE communication in the VERILOG algorithm CFFT implementation, with a certain reference value. <kobe> 在 2024-11-16 上传
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说明:基于wimax协议的低密度奇偶校验码LDPC的VERILOG实现,亲测可用。-WiMAX protocol based on the low density parity check code VERILOG LDPC implementation, pro test available. <kobe> 在 2024-11-16 上传
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说明:this program is done in verilog hdl and it is program of AND gate gate level modeling program-this program is done in verilog hdl and it is program of AND gate gate level modeling program <hetang> 在 2024-11-16 上传
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说明:this program is done in verilog hdl and it is program of AND gate DATA level modeling program-this program is done in verilog hdl and it is program of AND gate DATA level modeling program <hetang> 在 2024-11-16 上传
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说明:this program is done in verilog hdl and it is program of AND gate BEHVIORAL level modeling program-this program is done in verilog hdl and it is program of AND gate BEHVIORAL level modeling program <hetang> 在 2024-11-16 上传
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说明:this program is done in verilog hdl and it is program of NAND gate gate level modeling program-this program is done in verilog hdl and it is program of NAND gate gate level modeling program <hetang> 在 2024-11-16 上传
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说明:this program is done in verilog hdl and it is program of AND gate DATA level modeling program-this program is done in verilog hdl and it is program of AND gate DATA level modeling program <hetang> 在 2024-11-16 上传
| 大小:122kb | 下载:0