资源列表
[VHDL编程] jiaotongdeng
说明:理想状态的四路交通灯设计,用CPLD/FPGA驱动的,时间可以更改。-Ideal state of four traffic lights design, CPLD/FPGA-driven, time can be changed.<文辺> 在 2025-01-24 上传 | 大小:1kb | 下载:0
[VHDL编程] verilog_CPU
说明:用verilog写的RISC_CPU,描述文件很详尽,含有测试文件-Written by verilog RISC_CPU, very detailed descr iption of the file containing the test file<fyf> 在 2025-01-24 上传 | 大小:989kb | 下载:0
[VHDL编程] des_vhdl_code
说明:decription aes using vhdl code<dani.hassoun> 在 2025-01-24 上传 | 大小:137kb | 下载:0
[VHDL编程] dec_aes
说明:decription aes vhdl code for fpga<dani.hassoun> 在 2025-01-24 上传 | 大小:12kb | 下载:0
[VHDL编程] 8051_cpu_verilog
说明:The 8051 microcontroller is member of MCS-51 family, originally designed in the 1980 s by Intel. The 8051 has gained great popularity since its introduction and is estimated it is used in a large percentage of all embedd<spetrel> 在 2025-01-24 上传 | 大小:85kb | 下载:0
[VHDL编程] C_ADDSUB_V1_0
说明:针对xilinx器件的重要库文件,能够加快基于xilinx器件的工程开发,提高系统的性能。-For important library xilinx devices, to accelerate project development based on xilinx devices to improve system performance.<spetrel> 在 2025-01-24 上传 | 大小:4kb | 下载:0
[VHDL编程] C_COMPARE_V1_0
说明:针对Xilinx器件的关键库文件,该库文件实现了比较器的功能,能够加快项目的进度!-The key database file for Xilinx devices, the library implements the comparator function, to expedite the progress of the project!<spetrel> 在 2025-01-24 上传 | 大小:4kb | 下载:0