[VHDL编程] I2C_vhdl

说明： IMPORTANT NOTE: This design uses the I2C SCL signal as a clock. This requires that the SCL signal have clean, fast edges on both the rising and falling edges of this signal. Slow rise and fall times on this sign
<vijendra pal> 在 2025-03-07 上传 | 大小：830kb | 下载：0

[VHDL编程] manchester_verilog

说明： This design is targeted to the XCR3064XL-7VQ100C CoolRunner CPLD. This is a 3V, 64 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
<vijendra pal> 在 2025-03-07 上传 | 大小：10kb | 下载：0

[VHDL编程] manchester_vhdl

说明：This design is targeted to the XCR3064XL-7VQ100C CoolRunner CPLD. This is a 3V, 64 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
<vijendra pal> 在 2025-03-07 上传 | 大小：11kb | 下载：0

[VHDL编程] spi_cpld_vhdl

说明：The CoolRunner-II "Confuguring Xilinx FPGAs with SPI Flash Memories using CoolRunner-II CPLDs" reference design is based upon the STMicroelectronics SPI Flash memory M25P20. This design can be easily modified
<vijendra pal> 在 2025-03-07 上传 | 大小：431kb | 下载：0

[VHDL编程] uart_verilog

说明：The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection. This design is targeted to the XCR3128XL
<vijendra pal> 在 2025-03-07 上传 | 大小：5kb | 下载：0

[VHDL编程] uart_vhdl

说明：The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection. This design is targeted to the XCR3128XL
<vijendra pal> 在 2025-03-07 上传 | 大小：6kb | 下载：0

[VHDL编程] smartcard_vhdl

说明：Readme File for Smart Card Reader File Contents ************************************************************************* This zip file contains the following files: -- VHDL Source Files in Smartcard: To
<vijendra pal> 在 2025-03-07 上传 | 大小：515kb | 下载：0

[VHDL编程] project-05

说明：Project05.zip Memory.hdl
<Rosh> 在 2025-03-07 上传 | 大小：13kb | 下载：0

[VHDL编程] dvi_encoder_decoder_for---fpga

说明：dvi encoder and decoder in VHDL for FGPA developer.
<Tran Thanh> 在 2025-03-07 上传 | 大小：152kb | 下载：0

[VHDL编程] DE1-lab

说明：solution of lab 1 to lab 8 in DE1 lab exercises.
<Tran Thanh> 在 2025-03-07 上传 | 大小：32kb | 下载：0

[VHDL编程] function-of-adder32

说明：这是一个32 bits carry-select-addeer.It s very new.-this is an adder with the function of 32bits adder.
<谌敏飞> 在 2025-03-07 上传 | 大小：1kb | 下载：0

[VHDL编程] alu-4bit

说明：alu包含各种运算功能，有点事现对于其他的程序，面积较小-it has a smaller square compared with othe program.
<谌敏飞> 在 2025-03-07 上传 | 大小：1kb | 下载：0