资源列表
[其他嵌入式/单片机内容] carparking
说明:this for automatic car parking system it displays the space availability and also control the gate in parking area-this is for automatic car parking system it displays the space availability and also control the gate<jaggu> 在 2025-02-26 上传 | 大小:1kb | 下载:0
[其他嵌入式/单片机内容] NMEA0183_v1.1
说明:NMEA0183 报文解析 $GPZDA $GPGSA $GPGGA-NMEA0183 DECODER<KA22134> 在 2025-02-26 上传 | 大小:1kb | 下载:0
[单片机(51,AVR,MSP430等)] TIMER
说明:单片机C语言编程模板定时计数器,可以添加其他函数-Microcontroller C programming templates timer counters, you can add other functions<李小桐> 在 2025-02-26 上传 | 大小:1kb | 下载:0
[单片机(51,AVR,MSP430等)] INT.C
说明:单片机C语言编程模板定时计数器,可以添加函数-Microcontroller C programming templates timer counters, you can add a function<李小桐> 在 2025-02-26 上传 | 大小:1kb | 下载:0
[VHDL编程] FIR
说明:The first three examples illustrate the difference between RTL FSMD model (Finite State Machine with Datapath buildin) and RTL FSM + DataPath model. From view of RT level design, each digital design consists of a Control<dhanagopal> 在 2025-02-26 上传 | 大小:1kb | 下载:0
[VHDL编程] memory
说明:the memory program are used to design the fpga application for in very log module<dhanagopal> 在 2025-02-26 上传 | 大小:1kb | 下载:0
[VHDL编程] statemechine
说明:We are using parameters is the test bench and passing them to the state machine using parameter passing We are using tasks to control the flow of the testbench We are using hierarchical naming to access the state v<dhanagopal> 在 2025-02-26 上传 | 大小:1kb | 下载:0
[VHDL编程] uart
说明:the uart model is used to design the synthies and beherival model in verilog fpga<dhanagopal> 在 2025-02-26 上传 | 大小:1kb | 下载:0
[VHDL编程] clock1
说明:多功能数字钟实现闹铃,整点报时,校时,仿广播电台报时功能-multifuntional digital clock written in verilog<sliversnake> 在 2025-02-26 上传 | 大小:1kb | 下载:0
[嵌入式Linux] ttyMAX_read
说明:this for tty max chip read through external uart-this is for tty max chip read through external uart<nitin> 在 2025-02-26 上传 | 大小:1kb | 下载:0
[VHDL编程] tb_tx_modem
说明:test bench for tx modem to make simulation for ofdm based system<jhonny> 在 2025-02-26 上传 | 大小:1kb | 下载:0