资源列表
[VHDL编程] statemechine
说明:We are using parameters is the test bench and passing them to the state machine using parameter passing We are using tasks to control the flow of the testbench We are using hierarchical naming to access the state v<dhanagopal> 在 2025-03-22 上传 | 大小:1kb | 下载:0
[VHDL编程] uart
说明:the uart model is used to design the synthies and beherival model in verilog fpga<dhanagopal> 在 2025-03-22 上传 | 大小:1kb | 下载:0
[VHDL编程] clock1
说明:多功能数字钟实现闹铃,整点报时,校时,仿广播电台报时功能-multifuntional digital clock written in verilog<sliversnake> 在 2025-03-22 上传 | 大小:1kb | 下载:0
[嵌入式Linux] ttyMAX_read
说明:this for tty max chip read through external uart-this is for tty max chip read through external uart<nitin> 在 2025-03-22 上传 | 大小:1kb | 下载:0
[数值算法/人工智能] labsheet2part2
说明:find the largest substring in a string<Wiccan> 在 2025-03-22 上传 | 大小:1kb | 下载:0
[matlab例程] MidpointCircle
说明:Draw a circle in a matrix using the integer midpoint circle algorithm. Code does not miss or repeat pixels.<rohit> 在 2025-03-22 上传 | 大小:1kb | 下载:0