搜索资源列表
avi
- avi文件结构信息,从CSDN上面搜索来的!很好,很有用!已经用上项目!-avi file structure information, from english to CSDN above! very good, very useful! had the use of the item!
H264CODEC
- H264 encoder source code,very good -H264 encoder source code, very good
mux
- 每路输入数据与输出数据均为4位2进制数，当选择开关(至少3位)或输入数据发生变化时，输出数据也相应地变化。有兴趣的同学可以进一步扩充系统功能。-Each input data and output data are the four hexadecimal number 2, when the selector switch (at least 3) or input data changes, the output data chan
Verilog_example
- 本文件包括多路选择器器建模，译码器实验程序，加法器实验程序，比较器实验程序，计数器建模，I2C接口标准建模源码，串行接口RS232标准建模源码标准，LCM建模源码，时钟６分频源码，串并转化源码。 ，对于硬件设计初学者来说有一定的参考价值。-This document includes MUX device modeling, experimental procedure decoder, adder experimental pro
mux0710
- GSM 协议 0710多路复用的源码，可以在linux,windows环境使用。一个很明细的框架。-GSM protocol source multiplexer 0710 can be linux, windows environments. A very detailed fr a mework.
VxWorks_comC
- 基于VxWorks的端口控制实现.pdf ：介绍了嵌入式操作系统VxWorks下端1：2控制的两种实现方法：HOOK函数和MUX接1：2，并对两种实现方法的特点 和性能做了比较。-Based on VxWorks realize the port control. Pdf: introduction of the VxWorks embedded operating system to control the lower end
VHDL
- 数字系统设计中的全加器、10进制计数器、2-4译码器、摩尔状态机、2-1路选择器的源代码-Digital System Design full adder, 10 hexadecimal counter ,2-4 decoder, Moore state machine ,2-1 MUX source code
yibuqinglin
- 含异步清0和同步时钟使能的4位加法计数器 含计数使能,异步复位和计数值并行预置功能4位加法计数器,由实验图1所示,图中间是4位锁存器 rst是异步清信号,高电平有效 clk是锁存信号 D[3..0]是4位数据输入端.当ENA为 1 时,多路选择器将加1器的输出值加载于锁存器的数据端 当ENA为 0 时将"0000"加载于锁存器.-With asynchronous and synchronous clock clearance
x_guliverkli
- DirectShow开发工具包，包含Muxer, Parser, Reader, Source, Transform等几大类Filter事例。例：AviSplitter，MpegSplitter, OggSplitter, RealMediaSplitter, CddaReader, AudioSwitcher, Mpeg2decFilter等。-DirectShow Development Kit, including Muxer,
Verilog
- 很多实用的例程，包括触发器，译码器，多路选择器-A lot of useful routines, including the flip-flop, decoder, MUX
ACCE
- selects the mux channel and configures the MAX197 for second write pulse, written with ACQMOD = 0, termi- either unipolar or bipolar input range. A write pulse (WR nates acquisition and starts conversion on WR°Os r
ASM-TEST
- selects the mux channel and configures the MAX197 for second write pulse, written with ACQMOD = 0, termi- either unipolar or bipolar input range. A write pulse (WR nates acquisition and starts conversion on WR°Os r
ADC08090
- selects the mux channel and configures the MAX197 for second write pulse, written with ACQMOD = 0, termi- either unipolar or bipolar input range. A write pulse (WR nates acquisition and starts conversion on WR°Os r
DPLL(VHDL)
- 使用VHDL语言进行的数字锁相环的设计，里面有相关的文件，可以使用MUX+PLUS打开-The use of VHDL language of digital phase-locked loop design, there are relevant documents, you can use MUX+ PLUS Open
CDMA20001X-data
- DMA20001X提供了比IS95B更为丰富的数据业务，SCH数据速率可以从9.6kpbs到153.6kbps不等。吞吐量是衡量数据业务性能优劣的重要指标之一，对于网络的每一层（物理层、SDU层、Mux层、RLP层、PPP层、TCP/IP层、应用层）都有相应的吞吐量，虽然在物理层能够提供最大数据业务吞吐量为153.6+9.6＝163.2kpbs，但是由于层间复用，在数据包中增加了数据头，使得经过多层复用以后数据包长度变长；另外由于采用了
chap12
- 16个常用HDL编码打包上传 包括记数器，多路选择器，全加/半加器等，均通过modsim验证-16 commonly used HDL coding package upload includes counter, MUX, all add/semi-add, etc., are adopted to verify modsim
Mars_EP1C6F_fundemantal_demo
- FPGA 开发板源码。芯片为Mars EP1C6F.VHDL语言。可实现一些基本的功能。如乘法器、加法器、多路选择器等。-FPGA development board source. Chips for the Mars EP1C6F.VHDL language. Can achieve some of the basic functions. Such as multiplier, adder, such as MUX.
Mars_EP1C6F_Fundermental_demo(Verilog)
- FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。-FPGA development board supporting Verilog HDL code. Chips for the Mars EP1C6F. Are the basic source experiment. Including the adder, subtraction, and m
DDS_report_1
- 16:1 MUX usind 2 4:1 MUX Strutures
mux4_1
- 数字系统设计的编程，实现四选一的多路选择器，用ｖｅｒｉｌｏｇ实现。-The design of digital systems programming, to achieve the election of the four MUX, with the realization of verilog.