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- Basic gates and mux vhdl
UDP
- UDP of Dff and mux. COntains test bench also
vhdl__example_fza.ir
- useful vhdl example contain adder-mux-counter-ram-shifter-rom-flipflop-useful vhdl example contain adder-mux-counter-ram-shifter-rom-flipflop...
mux41
- 四选一数据选择器(四个输入选择一个输出)(Four select a data selector)
OTU_SOHMUX
- cctv otu soh mux source
mux 8_1
- 八选一数据选择器,hdl语言,基于FPGA,MAXⅡ,240T100C5.(Eight, select a data selector, HDL language, based on FPGA, MAX II, 240T100C5)
EFM8BB2_ADC
- ADC实例,用于模拟量采样实例,内部REF(The system is clocked by the internal 24.5 MHz oscillator divided by 1. // Timer 2 triggers a conversion on ADC0 on each overflow. The completion of // this conversionin turn triggers an interrup
mux_2to1_4to1_8to1
- design verilog hdl for mux 2to1, mux4to1, mux8to1
UNIVERSAL_SH_REG
- universal shift register using mux and d_ff
ffmpeg
- FFmpeg is the leading multimedia fr a mework, able to decode, encode, transcode, mux, demux, stream, filter and play pretty much anything that humans and machines have created. It supports the most obscure ancient format
DecoderAndMuxer
- Decoder and Muxer In an archive
mux41
- Multiplexer 4 input and 1 output for FPGA
mux_with multiplier
- mux to use with adder with full adder and half adder
EFM32外设模块—ADC-V1.00
- 模拟数字转换器(Analog to Digital Converter,简称 ADC)是 EFM32 片上模拟外设之一, 分辨率为 12 位时最大采样速率可达 1M Samples/s。其具有以下特性: z 可编程分辨率(6/8/12-bit); z 可选输入通道包括 8 个外部输入引脚和 7 个内部输入信号; z 单次转换和扫描转换两种工作模式; z 可选择使用内部参考电压或外部参考电压; z 支持硬件过采样。(The A
263295689sv_mux.tar
- verification of mux using system verilog
single_phase_inverter
- 学习使用,如果报错,需要更改Mux blocks used to create bus signals为error既可以(study using,please using above matlab2014a)
ads8688
- ADS8688 带 5V 单电源并支持双极输入的 16 位、8 通道、500Ksps ADC 具有集成模拟前端的 16 位 ADC 支持自动和手动两种扫描模式的 4 通道和 8 通道多路复用器 (MUX) 独立于通道的可编程输入范围: 双极:±10.24V、±5.12V 和 ±2.56V 单极:0V 到 10.24V 和 0V 到 5.12V 5V 模拟电源:1.65V 到 5V I/O 电源 恒定的阻性输入阻抗:1MΩ