搜索资源列表
Nios_SW_Tutorial_Cyclone_1C20
- 包括基于Cyclone1C20芯片NiosII软件开发的各种模块的测试例子，开发环境是基于NiosII IDE的，实际上就是eclipse开发-including chip-based Cyclone1C20 NiosII software modules developed by the test cases son, the development environment is based on NiosII IDE, in fac
CYCLONE2specialpin
- 在设计CYCLONE2的时候,有些特殊的管脚是需要特别注意的,该资料给出了全部的注意管脚.-CYCLONE2 the design of the times, some special pins are in need of special attention. The information given all the attention to the pin.
ALTERA_device_choice
- this a book about altera fpga device choice ,it is good for developing eda with fpga
Nios_Timer_DS1337
- 利用带有I2C总线接口的日历时钟芯片DS1337，在NIOS II嵌入式系统平台上实现一个实时时钟，并可在显示器上显示出预置的时分秒。硬件平台为Altera的Cyclone II版Nios II开发环境
Audio_DAC_FIFO
- altera的ip核，在sopcbuilder中添加后，在niosII IDE中可以用一条语句实现，音频解码的输出。-altera
fft_IPcore
- 这是一个fft的IP核，安装要求为quartus6.0以上。解压安装后可在quartus里例化使用，元件主要为cyclone和stratix,最大支持1024点的转换。
SmartSOPC_Board_Cyclone_1C6
- sopc开发板标准NIOSII模块，用于EP1C6Q240C8芯片（FPGA）-SOPC development board NIOSII standard module for EP1C6Q240C8 chip (FPGA)
lc2
- this a pack include source code for quartus 2. It is an implementation of the LC2. The LC-2 computer is described in Introduction to Computing Systems from Bits & Gates to C & Beyond by Yale Patt and Sanjay Patel, M
flash_erase
- FPGA flash 编程序,使用CYCLONE和FLASH-FPGA flash-programmed, the use of CYCLONE and FLASH
FPGA060815
- 重要代码,FPGA CYCLONE FLASH DRIVER
adder
- 基于ALTERA 公司cyclone系列FPGA的程序，verilog 实现加法器-ALTERA company based FPGA family of cyclone procedures, verilog adder realize
c2h_fft_cyclone_ii
- 在cycloneII里实现对FFT的硬件加速，包括所有的说明和源码-In cycloneII achieve hardware acceleration for FFT, including all instructions and source code
CycloneII_NiosII_2C35_Rev02_DB_P06_10906R_02_FAB.z
- CycloneII_NiosII的实验板资料，正在学习FPGA的可以参考一下-Experimental CycloneII_NiosII plate information, are learning FPGA
CycloneIII_SB_3C25
- Altera CycloneIII_Starter_Kit 开发板原理图-Altera CycloneIII_Starter_Kit development board schematics
cfg_cyclone_fpga
- 采用CPLD来培植ALTERA公司的CYCLONE系列FPGA，（AS，PS，FAS）可选-CPLD used to cultivate ALTERA company CYCLONE series FPGA, (AS, PS, FAS) optional
sdsdi
- DVB系统的SDI数据数据传输接口，FPGA设计实现-DVB system SDI data transmission interface, FPGA Design and Implementation
dpll_demo
- 一个实现简单的数字锁相环Verilog代码，本人借鉴网上现有的代码后经修改在Cyclone II上调通实现，里面有ModelSim仿真成功的波形图-A simple digital PLL Verilog code, I draw on-line after the existing code, as amended, pass upward in the Cyclone II realized, there are successfu
HC164
- 用verilog写的HC164的驱动程序，参考了Xilinx的经典算法，做了一点改进~~~很通用，是初学verilog以及FPGA开发很有用的一个程序！