搜索资源列表
Cyclone_Series_Device_Thermal_Resistance
- cyclone系列FPGA的串行设备阻抗匹配设计指南-cyclone series FPGA Design Guide impedance matching of serial devices
sopcfpga
- 一个Altera Cyclone PCI开发板的配套样板源代码-Sample source code for An Altera Cyclone PCI development board
cyclone_handbook
- Altera 公司生产的FPGA系列中的低端高性能产品cyclone一代用户手册,这个也能从Altera官方网站上下载。-Altera' s FPGA series production of low-end high-performance products cyclone generation, user manuals, this is also downloaded from the Altera website.
cyclone2_handbook
- Altera 公司生产的FPGA系列中的低端高性能产品cyclone二代用户手册,这个也能从Altera官方网站上下载。-Altera' s FPGA series production of low-end high-performance products cyclone II user' s manual, this is also downloaded from the Altera website.
protel_altera_pcb_sch_lib
- altera cyclone 系列的protel封装图，layout的哥们有用的~-altera cyclone series of protel package diagram, layout useful ~
EP3C120
- EP3C120的官方开发板原理图，cyclone iii 系列最大的FPGA.-EP3C120s official development board schematics, cyclone iii series of the largest FPGA.
FPGA_Clk
- 基于Cyclone EP1C6240C8 FPGA的时钟产生模块。主要用于为FPGA系统其他模块产生时钟信号。采用verilog编写。 使用计时器的方式产生时钟波形。 提供对于FPGA时钟的偶数分频、奇数分频、始终脉冲宽度等功能。-Based on Cyclone EP1C6240C8 FPGA' s clock generator module. Is mainly used for the FPGA system cl
FPGA_AD
- 基于 Cyclone EP1C6240C8 FPGA的ADS2807接口程序，主要用来使用FPGA控制ADS2807的采集。 采用FPGA来模拟ADS2807的时序来实现控制功能。 提供采样频率控制、AD通道转换、采样数据缓存等功能。-Cyclone EP1C6240C8 FPGA-based interface program of the ADS2807, ADS2807 is mainly used to control
FPGA_ADDA
- 基于 Cyclone EP1C6240C8的ADS2807，DAC2902 测试程序。主要用来使用FPGA控制ADC采集和DAC的输出，从而达到高频率信号处理的功能。首先从ADC2807采集数据，然后送给DAC2902输出。 采用FPGA口线模拟ADC2807和DAC2902的时序来实现。 提供ADC采样频率控制、DAC输出频率控制、输出波形控制、ADC通道转换、DAC通道转换等功能。-Based on Cyclone EP1C
nios_lcd_3c120
- Cyclone III FPGA Nios II LCD开发程序，包括QuartusII工程及Verilog源码。-Cyclone III FPGA Nios II LCD development process, including the QuartusII engineering and source code.
cycloneIII_useful_SCH
- cyclone III 原理图，很实用的原理图，找了很长时间才找到-cyclone III schematic, it is useful schematic, looking for a very long time to find
CyclonePLL
- Cyclone™ FPGA具有锁相环（PLL）和全局时钟网络，提供完整的时钟管理方案。Cyclone PLL具有时钟倍频和分频、相位偏移、可编程占空比和外部时钟输出，进行系统级的时钟管理和偏移控制。Altera® Quartus® II软件无需任何外部器件，就可以启用Cyclone PLL和相关功能。本文将介绍如何设计和使用Cyclone PLL功能。 PLL常用于同步内部器件时钟和外部时钟，使内部工作的时
VGA_v
- 基于 FPGA 的VGA显示控制器设计（采用Verilog 语言） 控制VGA显示模块 VGA_HS,VGA_VS1,VGA_BLANK时序的发生器。包括测试程序 采用ALTERA Cyclone II系列芯片EP2C8Q208C8N芯片测试成功。-module VGA(CLK_50,RST_N,VGA_HS,VGA_VS1,VGA_BLANK, VGA_CLK,VGA_SYNC,VGA_R,VGA_G,VGA
Bufor
- Circular buffer using a cyclone memory ( Quartus II and VHDL .)-Circular buffer using a cyclone memory ( Quartus II and VHDL .)
EP2C
- cyclone II的开发板原理图和pcb图-development kit sch and pcb file of cyclone II
EP2C35_PCI
- 文章描述了FPGA的CYCLONE II系列芯片的PCI的最小系统的相关参考资料，对于初学者有很大的帮助！-Article describes the CYCLONE II family of FPGA-chip PCI-minimum system-related references, very helpful for beginners!
testbench
- altera 最新的CYCLONE IV的pci-e核的testbench，VHDL源程序。-altera latest CYCLONE IV of the pci-e core testbench, VHDL source code.
zhuangtaiji
- 检测姓名序列的状态机。使用VERILOG编写。平台是QuartusII9.1。Cyclone -Detection of sequence state machine name. Prepared using VERILOG. Platform is QuartusII9.1. Cyclone III
meanFilter
- This is a variable length window averaging filter that uses an MCP3002 ADC with SPI interface to sample an analog input, and has a PWM that can be run through a low-pass filter to produce an analog output. The design was
cycloneiii_sb_3c25
- 这是ALTERA 公司Cyclone III的Cyclone III的EP3C25的原理图，对于学习FPGA有很大的帮助。-It is very usefull to learner,which learn Cyclone III-EP3C25,It could help you more easier escape it!