搜索资源列表
Push_Boxes
- 在Xilinx环境下编写的vhdl程序，实现推箱子的游戏任务，界面很漂亮。-Xilinx environment in the preparation of the VHDL program, realized the game viewing tasks, the interface is very beautiful.
addsub_core_
- hdl的8051核，不知道好不好用大家试试吧。xilinx公司的核-HDL 8051 nuclear, we know that is really useful to try it. Xilinx's nuclear
xapp195
- signed_mult乘法器通常用于DSP设计。但由于赛灵思的FPGA架构中包含有-signed_mult multiplier is used DSP design. But Xilinx FPGA architecture contains
clockbyvhdl
- 在xilinx的ise环境下用vhdl编写的一个时钟程序。-in the environment and ideally with the preparation of a VHDL clock procedures.
pwmvhdl
- 一个在xilinx的ise环境下编译仿真成功的pWM程序。-one of the Xilinx environment ideally compiler pWM success of the simulation procedures.
keybyise
- 一个在xilinx公司ise编译环境下仿真成功的键盘操作程序。-a company embarks on the environment and ideally compile successful simulation keyboard operations.
ddr_verilog_xilinx
- 该程序是在xilinx的FPGA上实现DDR_SDRAM接口，程序是用verylog语言写的-that the procedure was in Xilinx FPGA to achieve DDR_SDRAM interface, procedures used to write the language verylog
Memec_3SLC_Schematic_Rev1p2
- Xilinx 的Spartan3的原理图,老外画的,很值得研究 .-Xilinx Spartan3 the schematics, pictures of foreigners, is worth studies.
eisp_pc
- Xilinx Jtag Configuration source code, Support *.xsvf file-Xilinx Configuration source code, Support xsvf file*.
PicoBlaze_03292006
- 基于Xilinx PicoBlaze处理器内核的系统 源代码-based Xilinx PicoBlaze processor system source code
fixed_pointDivider
- 本人编写的定点除法器,开发软件为XILINX的ISE6.2,通过PAR仿真.-I prepared for the sentinel division, the development of software for the ISE6.2 Xilinx, PAR through simulation.
SS7160.ZIP
- 该代码为配合7号信令模块MK50H27的cpld(xilinx 95144)的逻辑代码,其中包括了VHDL及原理图.-the code to meet on the 7th of signaling modules MK50H27 cpld (Xilinx 95144 ) logic code, which included a schematic and VHDL.
xc9572_1
- xilinx xc9572 cpld 实现的伺服电机控制器，电机控制输出，和增量编码器读取。-Xilinx xc9572 cpld achieve servo motor controller, motor control output, Incremental encoder and the reader.
UserGuide
- xilinx的嵌入式开发xps的用户手册-Xilinx Embedded Development of the user manual xps
V4_FX_Mini_Module
- xilinx的嵌入式开发xps，virtex-4的mini开发板手册-Xilinx Embedded Development xps, Virtex-4 mini manual development board
S2P_xapp194
- VHDL，verilog串并转换源程序 Xilinx公司参考资料-VHDL, verilog Series and conversion company Xilinx reference source
manchester_base_on_verilog
- yon用硬件描述语言写的曼彻斯特编解码,并在Xilinx CPLD上的实现,内容齐全,是学习的好资料-yon hardware descr iption language used to write the Manchester encoding and decoding Xilinx CPLD and the realization that the complete study is a good information
taxiwork
- 介绍了基于FPGA的多功能计程车计价器的电路设计。该设计采用了可编程逻辑器件FPGA的ASIC设计，并基于超高速硬件描述语言VHDL在Xilinx公司的SpartanⅡ系列的2sc200PQ208-5芯片上编程实现了整个系统的控制部分，整个自动控制系统由四个模块构成：秒分频模块、控制模块、计量模块和译码显示模块。该设计不仅仅实现了显示计程车计费的功能，其多功能表现在它可以通过选择键选择显示计程车累计走的总路程和乘客乘载的时间。计时、计程
ISPdownload
- 各种JTAG：包括ALTERA、ARM、AVR、LATTICE、S52、XILINX。-various JTAG include : Altera, ARM, AVR, LATTICE, S52, XILINX.
VerilogHDLPLI
- Verilog HDL的PLI子程序接口，用于与用户C程序在2个方向上传输数据，可用xilinx ISE，quartusii或modelsim仿真，-Verilog HDL PLI subroutine interfaces, for C program with the user in the direction of two transmission of data, available xilinx ISE. quartusii