压缩包 : 45665989ptc.rar 列表
ptc\CVS\Root
ptc\CVS\Repository
ptc\CVS\Entries
ptc\bench\CVS\Root
ptc\bench\CVS\Repository
ptc\bench\CVS\Entries
ptc\bench\VHDL\CVS\Root
ptc\bench\VHDL\CVS\Repository
ptc\bench\VHDL\CVS\Entries
ptc\bench\verilog\CVS\Root
ptc\bench\verilog\CVS\Repository
ptc\bench\verilog\CVS\Entries
ptc\bench\verilog\clkrst.v
ptc\bench\verilog\tb_defines.v
ptc\bench\verilog\tb_tasks.v
ptc\bench\verilog\tb_top.v
ptc\bench\verilog\timescale.v
ptc\bench\verilog\wb_master.v
ptc\doc\CVS\Root
ptc\doc\CVS\Repository
ptc\doc\CVS\Entries
ptc\doc\ptc_spec.pdf
ptc\doc\src\CVS\Root
ptc\doc\src\CVS\Repository
ptc\doc\src\CVS\Entries
ptc\doc\src\ptc_spec.doc
ptc\fv\CVS\Root
ptc\fv\CVS\Repository
ptc\fv\CVS\Entries
ptc\lint\CVS\Root
ptc\lint\CVS\Repository
ptc\lint\CVS\Entries
ptc\lint\bin\CVS\Root
ptc\lint\bin\CVS\Repository
ptc\lint\bin\CVS\Entries
ptc\lint\log\CVS\Root
ptc\lint\log\CVS\Repository
ptc\lint\log\CVS\Entries
ptc\lint\out\CVS\Root
ptc\lint\out\CVS\Repository
ptc\lint\out\CVS\Entries
ptc\lint\run\CVS\Root
ptc\lint\run\CVS\Repository
ptc\lint\run\CVS\Entries
ptc\rtl\CVS\Root
ptc\rtl\CVS\Repository
ptc\rtl\CVS\Entries
ptc\rtl\VHDL\CVS\Root
ptc\rtl\VHDL\CVS\Repository
ptc\rtl\VHDL\CVS\Entries
ptc\rtl\verilog\CVS\Root
ptc\rtl\verilog\CVS\Repository
ptc\rtl\verilog\CVS\Entries
ptc\rtl\verilog\ptc_defines.v
ptc\rtl\verilog\ptc_top.v
ptc\sim\CVS\Root
ptc\sim\CVS\Repository
ptc\sim\CVS\Entries
ptc\sim\gate_sim\CVS\Root
ptc\sim\gate_sim\CVS\Repository
ptc\sim\gate_sim\CVS\Entries
ptc\sim\gate_sim\bin\CVS\Root
ptc\sim\gate_sim\bin\CVS\Repository
ptc\sim\gate_sim\bin\CVS\Entries
ptc\sim\gate_sim\log\CVS\Root
ptc\sim\gate_sim\log\CVS\Repository
ptc\sim\gate_sim\log\CVS\Entries
ptc\sim\gate_sim\out\CVS\Root
ptc\sim\gate_sim\out\CVS\Repository
ptc\sim\gate_sim\out\CVS\Entries
ptc\sim\gate_sim\run\CVS\Root
ptc\sim\gate_sim\run\CVS\Repository
ptc\sim\gate_sim\run\CVS\Entries
ptc\sim\gate_sim\src\CVS\Root
ptc\sim\gate_sim\src\CVS\Repository
ptc\sim\gate_sim\src\CVS\Entries
ptc\sim\rtl_sim\CVS\Root
ptc\sim\rtl_sim\CVS\Repository
ptc\sim\rtl_sim\CVS\Entries
ptc\sim\rtl_sim\bin\CVS\Root
ptc\sim\rtl_sim\bin\CVS\Repository
ptc\sim\rtl_sim\bin\CVS\Entries
ptc\sim\rtl_sim\bin\sim.sh
ptc\sim\rtl_sim\log\CVS\Root
ptc\sim\rtl_sim\log\CVS\Repository
ptc\sim\rtl_sim\log\CVS\Entries
ptc\sim\rtl_sim\out\CVS\Root
ptc\sim\rtl_sim\out\CVS\Repository
ptc\sim\rtl_sim\out\CVS\Entries
ptc\sim\rtl_sim\run\CVS\Root
ptc\sim\rtl_sim\run\CVS\Repository
ptc\sim\rtl_sim\run\CVS\Entries
ptc\sim\rtl_sim\src\CVS\Root
ptc\sim\rtl_sim\src\CVS\Repository
ptc\sim\rtl_sim\src\CVS\Entries
ptc\syn\CVS\Root
ptc\syn\CVS\Repository
ptc\syn\CVS\Entries
ptc\syn\bin\CVS\Root
ptc\syn\bin\CVS\Repository
ptc\syn\bin\CVS\Entries
ptc\syn\bin\cons_art_umc18.inc
ptc\syn\bin\cons_vs_umc18.inc
ptc\syn\bin\read_design.inc
ptc\syn\bin\reports.inc
ptc\syn\bin\save_design.inc
ptc\syn\bin\select_tech.inc
ptc\syn\bin\set_env.inc
ptc\syn\bin\tech_art_umc18.inc
ptc\syn\bin\tech_vs_umc18.inc
ptc\syn\bin\top_ptc.scr
ptc\syn\log\CVS\Root
ptc\syn\log\CVS\Repository
ptc\syn\log\CVS\Entries
ptc\syn\out\CVS\Root
ptc\syn\out\CVS\Repository
ptc\syn\out\CVS\Entries
ptc\syn\run\CVS\Root
ptc\syn\run\CVS\Repository
ptc\syn\run\CVS\Entries
ptc\syn\run\dodesign
ptc\syn\src\CVS\Root
ptc\syn\src\CVS\Repository
ptc\syn\src\CVS\Entries
ptc\sim\gate_sim\bin\CVS
ptc\sim\gate_sim\log\CVS
ptc\sim\gate_sim\out\CVS
ptc\sim\gate_sim\run\CVS
ptc\sim\gate_sim\src\CVS
ptc\sim\rtl_sim\bin\CVS
ptc\sim\rtl_sim\log\CVS
ptc\sim\rtl_sim\out\CVS
ptc\sim\rtl_sim\run\CVS
ptc\sim\rtl_sim\src\CVS
ptc\bench\VHDL\CVS
ptc\bench\verilog\CVS
ptc\doc\src\CVS
ptc\lint\bin\CVS
ptc\lint\log\CVS
ptc\lint\out\CVS
ptc\lint\run\CVS
ptc\rtl\VHDL\CVS
ptc\rtl\verilog\CVS
ptc\sim\gate_sim\CVS
ptc\sim\gate_sim\bin
ptc\sim\gate_sim\log
ptc\sim\gate_sim\out
ptc\sim\gate_sim\run
ptc\sim\gate_sim\src
ptc\sim\rtl_sim\CVS
ptc\sim\rtl_sim\bin
ptc\sim\rtl_sim\log
ptc\sim\rtl_sim\out
ptc\sim\rtl_sim\run
ptc\sim\rtl_sim\src
ptc\syn\bin\CVS
ptc\syn\log\CVS
ptc\syn\out\CVS
ptc\syn\run\CVS
ptc\syn\src\CVS
ptc\bench\CVS
ptc\bench\VHDL
ptc\bench\verilog
ptc\doc\CVS
ptc\doc\src
ptc\fv\CVS
ptc\lint\CVS
ptc\lint\bin
ptc\lint\log
ptc\lint\out
ptc\lint\run
ptc\rtl\CVS
ptc\rtl\VHDL
ptc\rtl\verilog
ptc\sim\CVS
ptc\sim\gate_sim
ptc\sim\rtl_sim
ptc\syn\CVS
ptc\syn\bin
ptc\syn\log
ptc\syn\out
ptc\syn\run
ptc\syn\src
ptc\CVS
ptc\bench
ptc\doc
ptc\fv
ptc\lint
ptc\rtl
ptc\sim
ptc\syn
ptc