文件名称:emif1_16bit_sdram_cpu01

  • 所属分类:
  • DSP编程
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  • 上传时间:
  • 2018-05-19
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  • 263kb
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  • 0次
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  • 酒*
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改演示例子配置TMS320F28377D如何配置EMIF1寄存器控制16bit的SDRAM存储器(//! This example configures EMIF1 in 16bit SDRAM mode.
//! This example uses CS0 (SDRAM) as chip enable.)
(系统自动生成,下载前可以参看下载内容)

下载文件列表

文件名大小更新时间
emif1_16bit_sdram_cpu01\ccs\.ccsproject 451 2016-07-19
emif1_16bit_sdram_cpu01\ccs\.cproject 26130 2016-07-19
emif1_16bit_sdram_cpu01\ccs\.project 2924 2016-07-19
emif1_16bit_sdram_cpu01\ccs\.settings\org.eclipse.cdt.codan.core.prefs 62 2016-07-19
emif1_16bit_sdram_cpu01\ccs\.settings\org.eclipse.cdt.debug.core.prefs 123 2016-07-19
emif1_16bit_sdram_cpu01\ccs\.settings\org.eclipse.core.resources.prefs 223 2016-07-19
emif1_16bit_sdram_cpu01\ccs\CPU1_RAM\ccsObjs.opt 380 2016-07-19
emif1_16bit_sdram_cpu01\ccs\CPU1_RAM\emif1_16bit_sdram.obj 24578 2016-08-02
emif1_16bit_sdram_cpu01\ccs\CPU1_RAM\emif1_16bit_sdram.pp 9854 2016-08-02
emif1_16bit_sdram_cpu01\ccs\CPU1_RAM\emif1_16bit_sdram_cpu01.map 86825 2016-08-02
emif1_16bit_sdram_cpu01\ccs\CPU1_RAM\emif1_16bit_sdram_cpu01.out 567900 2016-08-02
emif1_16bit_sdram_cpu01\ccs\CPU1_RAM\emif1_16bit_sdram_cpu01_linkInfo.xml 336826 2016-08-02
emif1_16bit_sdram_cpu01\ccs\CPU1_RAM\F2837xD_CodeStartBranch.obj 2019 2016-08-02
emif1_16bit_sdram_cpu01\ccs\CPU1_RAM\F2837xD_DefaultISR.obj 66205 2016-08-02
emif1_16bit_sdram_cpu01\ccs\CPU1_RAM\F2837xD_DefaultISR.pp 9209 2016-08-02
emif1_16bit_sdram_cpu01\ccs\CPU1_RAM\F2837xD_Emif.obj 49691 2016-08-02
emif1_16bit_sdram_cpu01\ccs\CPU1_RAM\F2837xD_Emif.pp 8855 2016-08-02
emif1_16bit_sdram_cpu01\ccs\CPU1_RAM\F2837xD_GlobalVariableDefs.obj 489036 2016-08-02
emif1_16bit_sdram_cpu01\ccs\CPU1_RAM\F2837xD_GlobalVariableDefs.pp 7085 2016-08-02
emif1_16bit_sdram_cpu01\ccs\CPU1_RAM\F2837xD_Gpio.obj 165486 2016-08-02
emif1_16bit_sdram_cpu01\ccs\CPU1_RAM\F2837xD_Gpio.pp 8855 2016-08-02
emif1_16bit_sdram_cpu01\ccs\CPU1_RAM\F2837xD_Ipc.obj 17637 2016-08-02
emif1_16bit_sdram_cpu01\ccs\CPU1_RAM\F2837xD_Ipc.pp 8967 2016-08-02
emif1_16bit_sdram_cpu01\ccs\CPU1_RAM\F2837xD_PieCtrl.obj 22733 2016-08-02
emif1_16bit_sdram_cpu01\ccs\CPU1_RAM\F2837xD_PieCtrl.pp 9032 2016-08-02
emif1_16bit_sdram_cpu01\ccs\CPU1_RAM\F2837xD_PieVect.obj 45791 2016-08-02
emif1_16bit_sdram_cpu01\ccs\CPU1_RAM\F2837xD_PieVect.pp 9032 2016-08-02
emif1_16bit_sdram_cpu01\ccs\CPU1_RAM\F2837xD_SysCtrl.obj 90029 2016-08-02
emif1_16bit_sdram_cpu01\ccs\CPU1_RAM\F2837xD_SysCtrl.pp 9032 2016-08-02
emif1_16bit_sdram_cpu01\ccs\CPU1_RAM\F2837xD_usDelay.obj 1682 2016-08-02
emif1_16bit_sdram_cpu01\ccs\CPU1_RAM\makefile 4600 2016-08-02
emif1_16bit_sdram_cpu01\ccs\CPU1_RAM\objects.mk 341 2016-07-19
emif1_16bit_sdram_cpu01\ccs\CPU1_RAM\sources.mk 1936 2016-07-19
emif1_16bit_sdram_cpu01\ccs\CPU1_RAM\subdir_rules.mk 8088 2016-08-02
emif1_16bit_sdram_cpu01\ccs\CPU1_RAM\subdir_vars.mk 3083 2016-08-02
emif1_16bit_sdram_cpu01\ccs\targetConfigs\TMS320F28377D.ccxml 1898 2016-07-19
emif1_16bit_sdram_cpu01\emif1_16bit_sdram.c 8693 2016-07-19
emif1_16bit_sdram_cpu01\ccs\.launches 0 2016-10-09
emif1_16bit_sdram_cpu01\ccs\.settings 0 2017-10-19
emif1_16bit_sdram_cpu01\ccs\CPU1_RAM 0 2017-10-19
emif1_16bit_sdram_cpu01\ccs\targetConfigs 0 2017-10-19
emif1_16bit_sdram_cpu01\ccs 0 2017-10-19
emif1_16bit_sdram_cpu01 0 2017-10-19

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