文件名称:purePLcode
介绍说明－－下载内容均来自于网络，请自行研究使用
基于ZYBO的纯PL编程，虽然加入了PS的IP但是并未对其进行编程。基本功能为通过switch0控制led的点亮与否，完全通过PL部分实现。下载代码是即使只下载FPGA也可以。-Based ZYBO pure PL programming, although the added PS of IP but did not program them. The basic function of the lighting control led by switch0 or not fully realized by PL part. Download the code even if only FPGA can also be downloaded.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
project_5\project_5.cache
.........\...............\compile_simlib
.........\...............\..............\activehdl
.........\...............\..............\ies
.........\...............\..............\modelsim
.........\...............\..............\questa
.........\...............\..............\riviera
.........\...............\..............\vcs
.........\...............\wt
.........\...............\..\java_command_handlers.wdf
.........\...............\..\project.wpc
.........\...............\..\synthesis.wdf
.........\...............\..\synthesis_details.wdf
.........\...............\..\webtalk_pa.xml
.........\project_5.hw
.........\............\project_5.lpr
.........\project_5.ip_user_files
.........\.......................\ipstatic
.........\project_5.runs
.........\..............\.jobs
.........\..............\.....\vrs_config_1.xml
.........\..............\.....\vrs_config_10.xml
.........\..............\.....\vrs_config_11.xml
.........\..............\.....\vrs_config_12.xml
.........\..............\.....\vrs_config_13.xml
.........\..............\.....\vrs_config_14.xml
.........\..............\.....\vrs_config_15.xml
.........\..............\.....\vrs_config_16.xml
.........\..............\.....\vrs_config_17.xml
.........\..............\.....\vrs_config_18.xml
.........\..............\.....\vrs_config_19.xml
.........\..............\.....\vrs_config_2.xml
.........\..............\.....\vrs_config_20.xml
.........\..............\.....\vrs_config_21.xml
.........\..............\.....\vrs_config_22.xml
.........\..............\.....\vrs_config_23.xml
.........\..............\.....\vrs_config_3.xml
.........\..............\.....\vrs_config_4.xml
.........\..............\.....\vrs_config_5.xml
.........\..............\.....\vrs_config_6.xml
.........\..............\.....\vrs_config_7.xml
.........\..............\.....\vrs_config_8.xml
.........\..............\.....\vrs_config_9.xml
.........\..............\impl_1
.........\..............\......\.init_design.begin.rst
.........\..............\......\.init_design.end.rst
.........\..............\......\.opt_design.begin.rst
.........\..............\......\.opt_design.end.rst
.........\..............\......\.place_design.begin.rst
.........\..............\......\.place_design.end.rst
.........\..............\......\.route_design.begin.rst
.........\..............\......\.route_design.end.rst
.........\..............\......\.vivado.begin.rst
.........\..............\......\.vivado.end.rst
.........\..............\......\.Vivado_Implementation.queue.rst
.........\..............\......\.write_bitstream.begin.rst
.........\..............\......\.write_bitstream.end.rst
.........\..............\......\.Xil
.........\..............\......\design_1_wrapper.bit
.........\..............\......\design_1_wrapper.hwdef
.........\..............\......\design_1_wrapper.sysdef
.........\..............\......\design_1_wrapper.tcl
.........\..............\......\design_1_wrapper.vdi
.........\..............\......\design_1_wrapper_3612.backup.vdi
.........\..............\......\design_1_wrapper_8324.backup.vdi
.........\..............\......\design_1_wrapper_9056.backup.vdi
.........\..............\......\design_1_wrapper_9724.backup.vdi
.........\..............\......\design_1_wrapper_clock_utilization_routed.rpt
.........\..............\......\design_1_wrapper_control_sets_placed.rpt
.........\..............\......\design_1_wrapper_drc_opted.rpt
.........\..............\......\design_1_wrapper_drc_routed.pb
.........\..............\......\design_1_wrapper_drc_routed.rpt
.........\..............\......\design_1_wrapper_io_placed.rpt
.........\..............\......\design_1_wrapper_opt.dcp
.........\..............\......\design_1_wrapper_placed.dcp
.........\..............\......\design_1_wrapper_power_routed.rpt
.........\..............\......\design_1_wrapper_power_summary_routed.pb
.........\..............\......\design_1_wrapper_route_status.pb
.........\..............\......\design_1_wrapper_route_status.rpt
.........\..............\......\design_1_wrapper_routed.dcp