文件名称:asyn_fifo
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本文同步FIFO为TPRAM（两端口RAM，一读一写）。有详细verilog 程序以及说明-FIFO divided by clock domain can be divided into synchronous and asynchronous FIFO FIFO, FIFO read and write only one clock synchronous, asynchronous FIFO read and write were a clock. FIFO divided by port can be divided into TPRAM, DPRAM, TPRAM read one each port, a port read-only, write-only another port, DPRAM read each one each port, each port can either be read. This article synchronous FIFO is TPRAM (two-port RAM, a read a write).
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下载文件列表
asyn_fifo
.........\RTL
.........\...\asyn_fifo.jpg
.........\...\asyn_fifo.v
.........\...\asyn_fifo.v.bak
.........\...\bin2gray.v
.........\...\gray2bin.v
.........\...\syn_fifo.v.bak
.........\asyn_fifo.asm.rpt
.........\asyn_fifo.done
.........\asyn_fifo.fit.rpt
.........\asyn_fifo.fit.smsg
.........\asyn_fifo.fit.summary
.........\asyn_fifo.flow.rpt
.........\asyn_fifo.map.rpt
.........\asyn_fifo.map.smsg
.........\asyn_fifo.map.summary
.........\asyn_fifo.pin
.........\asyn_fifo.pof
.........\asyn_fifo.qpf
.........\asyn_fifo.qpf.bak
.........\asyn_fifo.qsf
.........\asyn_fifo.qsf.bak
.........\asyn_fifo.qws
.........\asyn_fifo.sof
.........\asyn_fifo.tan.rpt
.........\asyn_fifo.tan.summary
.........\db
.........\..\asyn_fifo.asm.qmsg
.........\..\asyn_fifo.cbx.xml
.........\..\asyn_fifo.cmp.ecobp
.........\..\asyn_fifo.cmp.rdb
.........\..\asyn_fifo.cmp0.ddb
.........\..\asyn_fifo.cmp2.ddb
.........\..\asyn_fifo.cmp_bb.cdb
.........\..\asyn_fifo.cmp_bb.hdb
.........\..\asyn_fifo.cmp_bb.logdb
.........\..\asyn_fifo.cmp_bb.rcf
.........\..\asyn_fifo.db_info
.........\..\asyn_fifo.dbp
.........\..\asyn_fifo.eco.cdb
.........\..\asyn_fifo.fit.qmsg
.........\..\asyn_fifo.hier_info
.........\..\asyn_fifo.hif
.........\..\asyn_fifo.map.bpm
.........\..\asyn_fifo.map.cdb
.........\..\asyn_fifo.map.ecobp
.........\..\asyn_fifo.map.hdb
.........\..\asyn_fifo.map.logdb
.........\..\asyn_fifo.map.qmsg
.........\..\asyn_fifo.map_bb.cdb
.........\..\asyn_fifo.map_bb.hdb
.........\..\asyn_fifo.map_bb.logdb
.........\..\asyn_fifo.pre_map.cdb
.........\..\asyn_fifo.pre_map.hdb
.........\..\asyn_fifo.psp
.........\..\asyn_fifo.pss
.........\..\asyn_fifo.rpp.qmsg
.........\..\asyn_fifo.rtlv.hdb
.........\..\asyn_fifo.rtlv_sg.cdb
.........\..\asyn_fifo.rtlv_sg_swap.cdb
.........\..\asyn_fifo.sgate.rvd
.........\..\asyn_fifo.sgate_sm.rvd
.........\..\asyn_fifo.sgdiff.cdb
.........\..\asyn_fifo.sgdiff.hdb
.........\..\asyn_fifo.sld_design_entry.sci
.........\..\asyn_fifo.sld_design_entry_dsc.sci
.........\..\asyn_fifo.syn_hier_info
.........\..\asyn_fifo.tan.qmsg
.........\..\asyn_fifo.tis_db_list.ddb
.........\..\gray2bin.db_info
.........\..\gray2bin.eco.cdb
.........\..\gray2bin.sld_design_entry.sci
.........\..\prev_cmp_asyn_fifo.asm.qmsg
.........\..\prev_cmp_asyn_fifo.fit.qmsg
.........\..\prev_cmp_asyn_fifo.map.qmsg
.........\..\prev_cmp_asyn_fifo.qmsg
.........\..\prev_cmp_asyn_fifo.tan.qmsg
.........\..\prev_cmp_syn_fifo.map.qmsg
.........\..\prev_cmp_syn_fifo.qmsg
.........\..\syn_fifo.cbx.xml
.........\..\syn_fifo.cmp.rdb
.........\..\syn_fifo.db_info
.........\..\syn_fifo.dbp
.........\..\syn_fifo.eco.cdb
.........\..\syn_fifo.hier_info
.........\..\syn_fifo.hif
.........\..\syn_fifo.map.bpm
.........\..\syn_fifo.map.cdb
.........\..\syn_fifo.map.ecobp
.........\..\syn_fifo.map.hdb
.........\..\syn_fifo.map.logdb
.........\..\syn_fifo.map.qmsg
.........\..\syn_fifo.map_bb.cdb
.........\..\syn_fifo.map_bb.hdb
.........\..\syn_fifo.map_bb.logdb
.........\..\syn_fifo.pre_map.cdb
.........\..\syn_fifo.pre_map.hdb
.........\..\syn_fifo.psp
.........\..\syn_fifo.pss