文件名称:digtal_clock
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FPGA实现数字钟VHDL语言编写,包涵整点报时，清零，调时调分等功能-FPGA digital clock VHDL language, includes the whole point timekeeping, cleared when the transfer function of adjusting grading
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下载文件列表
digtal_clock\baoshi.bsf
............\baoshi.vhd
............\baoshi.vhd.bak
............\db\digtal_clock.ae.hdb
............\..\digtal_clock.asm.qmsg
............\..\digtal_clock.asm.rdb
............\..\digtal_clock.asm_labs.ddb
............\..\digtal_clock.cbx.xml
............\..\digtal_clock.cmp.bpm
............\..\digtal_clock.cmp.cbp
............\..\digtal_clock.cmp.cdb
............\..\digtal_clock.cmp.ecobp
............\..\digtal_clock.cmp.hdb
............\..\digtal_clock.cmp.kpt
............\..\digtal_clock.cmp.logdb
............\..\digtal_clock.cmp.rdb
............\..\digtal_clock.cmp_merge.kpt
............\..\digtal_clock.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
............\..\digtal_clock.cuda_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
............\..\digtal_clock.db_info
............\..\digtal_clock.eco.cdb
............\..\digtal_clock.eds_overflow
............\..\digtal_clock.fit.qmsg
............\..\digtal_clock.fnsim.hdb
............\..\digtal_clock.fnsim.qmsg
............\..\digtal_clock.hier_info
............\..\digtal_clock.hif
............\..\digtal_clock.lpc.html
............\..\digtal_clock.lpc.rdb
............\..\digtal_clock.lpc.txt
............\..\digtal_clock.map.bpm
............\..\digtal_clock.map.cdb
............\..\digtal_clock.map.ecobp
............\..\digtal_clock.map.hdb
............\..\digtal_clock.map.kpt
............\..\digtal_clock.map.logdb
............\..\digtal_clock.map.qmsg
............\..\digtal_clock.map_bb.cdb
............\..\digtal_clock.map_bb.hdb
............\..\digtal_clock.map_bb.logdb
............\..\digtal_clock.pre_map.cdb
............\..\digtal_clock.pre_map.hdb
............\..\digtal_clock.rpp.qmsg
............\..\digtal_clock.rtlv.hdb
............\..\digtal_clock.rtlv_sg.cdb
............\..\digtal_clock.rtlv_sg_swap.cdb
............\..\digtal_clock.sgate.rvd
............\..\digtal_clock.sgate_sm.rvd
............\..\digtal_clock.sgdiff.cdb
............\..\digtal_clock.sgdiff.hdb
............\..\digtal_clock.sim.cvwf
............\..\digtal_clock.sim.hdb
............\..\digtal_clock.sim.qmsg
............\..\digtal_clock.sim.rdb
............\..\digtal_clock.sld_design_entry.sci
............\..\digtal_clock.sld_design_entry_dsc.sci
............\..\digtal_clock.smart_action.txt
............\..\digtal_clock.sta.qmsg
............\..\digtal_clock.sta.rdb
............\..\digtal_clock.sta_cmp.8_slow_1200mv_85c.tdb
............\..\digtal_clock.syn_hier_info
............\..\digtal_clock.tiscmp.fast_1200mv_0c.ddb
............\..\digtal_clock.tiscmp.slow_1200mv_0c.ddb
............\..\digtal_clock.tiscmp.slow_1200mv_85c.ddb
............\..\digtal_clock.tis_db_list.ddb
............\..\logic_util_heursitic.dat
............\..\prev_cmp_digtal_clock.asm.qmsg
............\..\prev_cmp_digtal_clock.fit.qmsg
............\..\prev_cmp_digtal_clock.map.qmsg
............\..\prev_cmp_digtal_clock.qmsg
............\..\prev_cmp_digtal_clock.sim.qmsg
............\..\prev_cmp_digtal_clock.sta.qmsg
............\..\wed.wsf
............\digtal_clock.asm.rpt
............\digtal_clock.bdf
............\digtal_clock.cdf
............\digtal_clock.done
............\digtal_clock.dpf
............\digtal_clock.fit.rpt
............\digtal_clock.fit.smsg
............\digtal_clock.fit.summary
............\digtal_clock.flow.rpt
............\digtal_clock.map.rpt
............\digtal_clock.map.summary
............\digtal_clock.pin
............\digtal_clock.qpf
............\digtal_clock.qsf
............\digtal_clock.qws
............\digtal_clock.sim.rpt
............\digtal_clock.sof
............\digtal_clock.sta.rpt
............\digtal_clock.sta.summary
............\display.bsf
............\display.vhd
............\display.vhd.bak
............\display.vwf
............\div.bsf
............\div.vhd
............\div.vhd.bak
............\div.vwf