文件名称:UART
介绍说明－－下载内容均来自于网络，请自行研究使用
A sample that describe how to make wiring between modules using verilog ,it contain two stages of inverter of SW1 as input and LD7 as output
(系统自动生成,下载前可以参看下载内容)
下载文件列表
a\a.ise
.\a.ise_ISE_Backup
.\aa.v
.\aa_summary.html
.\genExpectedResults.cmd
.\isim\work\glbl\glbl.h
.\....\....\....\mingw\glbl.obj
.\....\....\hdllib.ref
.\....\....\hdpdeps.ref
.\....\....\test__bench\mingw\test__bench.obj
.\....\....\...........\test__bench.h
.\....\....\...........\xsimtest__bench.cpp
.\....\....\uart\mingw\uart.obj
.\....\....\....\uart.h
.\....\....\vlg27\test__bench.bin
.\....\....\....D\glbl.bin
.\....\....\...48\uart.bin
.\....\....\...5B\_u_a_r_t__bench.bin
.\....\....\_u_a_r_t__bench\mingw\_u_a_r_t__bench.obj
.\....\....\...............\xsim_u_a_r_t__bench.cpp
.\....\....\...............\_u_a_r_t__bench.h
.\isim.cmd
.\isim.hdlsourcefiles
.\isim.log
.\.....tmp_save\_1
.\isimwavedata.xwv
.\prjname.lso
.\results.txt
.\test_bench.ano
.\test_bench.ant
.\test_bench.jhd
.\test_bench.tbw
.\test_bench.tfw
.\test_bench.xwv
.\test_bench.xwv_bak
.\test_bench_beh.prj
.\test_bench_bencher.prj
.\test_bench_gen.prj
.\test_bench_isim_beh.exe
.\test_bench_tbxr.exe
.\tmpRTVStore.xwv
.\uart.bgn
.\uart.bit
.\uart.bld
.\uart.cmd_log
.\uart.drc
.\uart.lfp
.\uart.lso
.\uart.ncd
.\uart.ngc
.\uart.ngd
.\uart.ngr
.\uart.pad
.\uart.par
.\uart.pcf
.\uart.prj
.\uart.stx
.\uart.syr
.\uart.twr
.\uart.twx
.\uart.ucf
.\uart.unroutes
.\uart.ut
.\uart.xpi
.\uart.xst
.\UART_bench.ano
.\UART_bench.ant
.\UART_bench.jhd
.\UART_bench.tbw
.\UART_bench.tfw
.\UART_bench.xwv
.\UART_bench.xwv_bak
.\UART_bench_bencher.prj
.\UART_bench_gen.prj
.\UART_bench_tbxr.exe
.\uart_last_par.ncd
.\uart_map.mrp
.\uart_map.ncd
.\uart_map.ngm
.\uart_pad.csv
.\uart_pad.txt
.\uart_summary.html
.\uart_vhdl.prj
.\xilinxsim.ini
.\.st\work\hdllib.ref
.\...\....\vlg48\uart.bin
.\_impact.cmd
.\_impact.log
.\.ngo\netlist.lst
.\_pace.ucf
.\.xmsgs\bitgen.xmsgs
.\......\fuse.xmsgs
.\......\map.xmsgs
.\......\ngdbuild.xmsgs
.\......\par.xmsgs
.\......\trce.xmsgs
.\......\xst.xmsgs
.\xst\dump.xst\uart.prj\ngx\notopt
.\...\........\........\...\opt
.\isim\work\glbl\mingw
.\a.ise_ISE_Backup
.\aa.v
.\aa_summary.html
.\genExpectedResults.cmd
.\isim\work\glbl\glbl.h
.\....\....\....\mingw\glbl.obj
.\....\....\hdllib.ref
.\....\....\hdpdeps.ref
.\....\....\test__bench\mingw\test__bench.obj
.\....\....\...........\test__bench.h
.\....\....\...........\xsimtest__bench.cpp
.\....\....\uart\mingw\uart.obj
.\....\....\....\uart.h
.\....\....\vlg27\test__bench.bin
.\....\....\....D\glbl.bin
.\....\....\...48\uart.bin
.\....\....\...5B\_u_a_r_t__bench.bin
.\....\....\_u_a_r_t__bench\mingw\_u_a_r_t__bench.obj
.\....\....\...............\xsim_u_a_r_t__bench.cpp
.\....\....\...............\_u_a_r_t__bench.h
.\isim.cmd
.\isim.hdlsourcefiles
.\isim.log
.\.....tmp_save\_1
.\isimwavedata.xwv
.\prjname.lso
.\results.txt
.\test_bench.ano
.\test_bench.ant
.\test_bench.jhd
.\test_bench.tbw
.\test_bench.tfw
.\test_bench.xwv
.\test_bench.xwv_bak
.\test_bench_beh.prj
.\test_bench_bencher.prj
.\test_bench_gen.prj
.\test_bench_isim_beh.exe
.\test_bench_tbxr.exe
.\tmpRTVStore.xwv
.\uart.bgn
.\uart.bit
.\uart.bld
.\uart.cmd_log
.\uart.drc
.\uart.lfp
.\uart.lso
.\uart.ncd
.\uart.ngc
.\uart.ngd
.\uart.ngr
.\uart.pad
.\uart.par
.\uart.pcf
.\uart.prj
.\uart.stx
.\uart.syr
.\uart.twr
.\uart.twx
.\uart.ucf
.\uart.unroutes
.\uart.ut
.\uart.xpi
.\uart.xst
.\UART_bench.ano
.\UART_bench.ant
.\UART_bench.jhd
.\UART_bench.tbw
.\UART_bench.tfw
.\UART_bench.xwv
.\UART_bench.xwv_bak
.\UART_bench_bencher.prj
.\UART_bench_gen.prj
.\UART_bench_tbxr.exe
.\uart_last_par.ncd
.\uart_map.mrp
.\uart_map.ncd
.\uart_map.ngm
.\uart_pad.csv
.\uart_pad.txt
.\uart_summary.html
.\uart_vhdl.prj
.\xilinxsim.ini
.\.st\work\hdllib.ref
.\...\....\vlg48\uart.bin
.\_impact.cmd
.\_impact.log
.\.ngo\netlist.lst
.\_pace.ucf
.\.xmsgs\bitgen.xmsgs
.\......\fuse.xmsgs
.\......\map.xmsgs
.\......\ngdbuild.xmsgs
.\......\par.xmsgs
.\......\trce.xmsgs
.\......\xst.xmsgs
.\xst\dump.xst\uart.prj\ngx\notopt
.\...\........\........\...\opt
.\isim\work\glbl\mingw