文件名称:uart_rx
- 所属分类：
- 其他嵌入式/单片机内容
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 521kb
- 下载次数：
- 0次
- 提 供 者：
- w***
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
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actel A3P250 fpga用VERILOG HDL语言实现串口功能的源代码-actel A3P250 fpga with VERILOG HDL Serial functional language source code
(系统自动生成,下载前可以参看下载内容)
下载文件列表
uart_rx
.......\component
.......\constraint
.......\coreconsole
.......\designer
.......\........\impl1
.......\........\.....\ada00192-1.tmp
.......\........\.....\ada00192-3.tmp
.......\........\.....\ada00552-3.tmp
.......\........\.....\ada00552-5.tmp
.......\........\.....\ada01764-2.tmp
.......\........\.....\ada01764-4.tmp
.......\........\.....\assert.log
.......\........\.....\designer.log
.......\........\.....\rcvr.adb
.......\........\.....\rcvr.dtf
.......\........\.....\........\verify.log
.......\........\.....\rcvr.ide_des
.......\........\.....\rcvr.lok
.......\........\.....\rcvr.stp
.......\........\.....\rcvr.tcl
.......\........\.....\rcvr_1.ide_des
.......\........\.....\rcvr_1_fp
.......\........\.....\.........\$$FlashPro_FPBBALTLPT1.L$$
.......\........\.....\.........\rcvr.log
.......\........\.....\.........\rcvr.pro
.......\........\.....\rcvr_fp
.......\........\.....\.......\rcvr.pro
.......\........\.....\simulation
.......\........\.....\unsav.lok
.......\........\.....\unsav001.lok
.......\hdl
.......\...\rcvr.v
.......\...\waveperl.log
.......\phy_synthesis
.......\simulation
.......\..........\meminit.dat
.......\..........\modelsim.ini
.......\..........\modelsim.ini.sav
.......\smartgen
.......\........\smartgen.aws
.......\stimulus
.......\synthesis
.......\.........\.recordref
.......\.........\rcvr.areasrr
.......\.........\rcvr.edn
.......\.........\rcvr.map
.......\.........\rcvr.sdf
.......\.........\rcvr.srd
.......\.........\rcvr.srm
.......\.........\rcvr.srr
.......\.........\rcvr.srs
.......\.........\rcvr.tlg
.......\.........\rcvr_sdc.sdc
.......\.........\rcvr_syn.prj
.......\.........\stdout.log
.......\.........\syntmp
.......\.........\......\rcvr.msg
.......\.........\......\rcvr.plg
.......\.........\traplog.tlg
.......\uart_rx.prj
.......\uart_rx.prj.convert.7.3.bak
.......\viewdraw
.......\........\sch
.......\........\sym
.......\........\vf
.......\........\..\project.lst
.......\........\viewdraw.ini
.......\........\wir
.......\component
.......\constraint
.......\coreconsole
.......\designer
.......\........\impl1
.......\........\.....\ada00192-1.tmp
.......\........\.....\ada00192-3.tmp
.......\........\.....\ada00552-3.tmp
.......\........\.....\ada00552-5.tmp
.......\........\.....\ada01764-2.tmp
.......\........\.....\ada01764-4.tmp
.......\........\.....\assert.log
.......\........\.....\designer.log
.......\........\.....\rcvr.adb
.......\........\.....\rcvr.dtf
.......\........\.....\........\verify.log
.......\........\.....\rcvr.ide_des
.......\........\.....\rcvr.lok
.......\........\.....\rcvr.stp
.......\........\.....\rcvr.tcl
.......\........\.....\rcvr_1.ide_des
.......\........\.....\rcvr_1_fp
.......\........\.....\.........\$$FlashPro_FPBBALTLPT1.L$$
.......\........\.....\.........\rcvr.log
.......\........\.....\.........\rcvr.pro
.......\........\.....\rcvr_fp
.......\........\.....\.......\rcvr.pro
.......\........\.....\simulation
.......\........\.....\unsav.lok
.......\........\.....\unsav001.lok
.......\hdl
.......\...\rcvr.v
.......\...\waveperl.log
.......\phy_synthesis
.......\simulation
.......\..........\meminit.dat
.......\..........\modelsim.ini
.......\..........\modelsim.ini.sav
.......\smartgen
.......\........\smartgen.aws
.......\stimulus
.......\synthesis
.......\.........\.recordref
.......\.........\rcvr.areasrr
.......\.........\rcvr.edn
.......\.........\rcvr.map
.......\.........\rcvr.sdf
.......\.........\rcvr.srd
.......\.........\rcvr.srm
.......\.........\rcvr.srr
.......\.........\rcvr.srs
.......\.........\rcvr.tlg
.......\.........\rcvr_sdc.sdc
.......\.........\rcvr_syn.prj
.......\.........\stdout.log
.......\.........\syntmp
.......\.........\......\rcvr.msg
.......\.........\......\rcvr.plg
.......\.........\traplog.tlg
.......\uart_rx.prj
.......\uart_rx.prj.convert.7.3.bak
.......\viewdraw
.......\........\sch
.......\........\sym
.......\........\vf
.......\........\..\project.lst
.......\........\viewdraw.ini
.......\........\wir