文件名称:sent_receive
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这是一个介绍32位RISC处理器软核的设计与验证-Introduction This is a soft 32-bit RISC processor core design and verification
(系统自动生成,下载前可以参看下载内容)
下载文件列表
sent_receive
............\automake.log
............\fa1_tbw.ant
............\fa1_tbw.tbw
............\fa1_tbw.vhw
............\fa1_tbw.xwv
............\fa1_tbw.xwv_bak
............\fa1_tbw_bencher.prj
............\fa2_tbw.ant
............\fa2_tbw.fdo
............\fa2_tbw.tbw
............\fa2_tbw.udo
............\fa2_tbw.vhw
............\fa2_tbw.xwv
............\fa2_tbw.xwv_bak
............\fa2_tbw_bencher.prj
............\fa_tbw.ano
............\fa_tbw.ant
............\fa_tbw.fdo
............\fa_tbw.isim_beh_exe
............\fa_tbw.isim_beh_log
............\fa_tbw.isim_beh_prj
............\fa_tbw.isim_gen_exe
............\fa_tbw.isim_gen_prj
............\fa_tbw.jhd
............\fa_tbw.tbw
............\fa_tbw.udo
............\fa_tbw.vhw
............\fa_tbw.xwv
............\fa_tbw.xwv_bak
............\fa_tbw_beh.prj
............\fa_tbw_bencher.prj
............\fa_tbw_gen.prj
............\fa_tbw_isim_beh.exe
............\fa_tbw_tbxr.exe
............\fa_v.cmd_log
............\fa_v.lso
............\fa_v.ngc
............\fa_v.ngr
............\fa_v.prj
............\fa_v.spl
............\fa_v.stx
............\fa_v.sym
............\fa_v.syr
............\fa_v.vhd
............\fa_v_summary.html
............\isim
............\....\work
............\....\....\fa_tbw
............\....\....\......\entity.cpp
............\....\....\......\entity.h
............\....\....\......\mingw
............\....\....\......\.....\testbench_arch.obj
............\....\....\......\testbench_arch.h
............\....\....\......\xsimtestbench_arch.cpp
............\....\....\fa_v
............\....\....\....\behavioral.h
............\....\....\....\entity.cpp
............\....\....\....\entity.h
............\....\....\....\mingw
............\....\....\....\.....\behavioral.obj
............\....\....\hdllib.ref
............\....\....\hdpdeps.ref
............\....\....\rcv_tbw
............\....\....\.......\entity.cpp
............\....\....\.......\entity.h
............\....\....\.......\mingw
............\....\....\.......\.....\testbench_arch.obj
............\....\....\.......\testbench_arch.h
............\....\....\.......\xsimtestbench_arch.cpp
............\....\....\rcv_v
............\....\....\.....\behavioral.h
............\....\....\.....\entity.cpp
............\....\....\.....\entity.h
............\....\....\.....\mingw
............\....\....\.....\.....\behavioral.obj
............\....\....\sent_receive_sch
............\....\....\................\behavioral.h
............\....\....\................\entity.cpp
............\....\....\................\entity.h
............\....\....\................\mingw
............\....\....\................\.....\behavioral.obj
............\....\....\sent_receive_tbw
............\....\....\................\entity.cpp
............\....\....\................\entity.h
............\....\....\................\mingw
............\....\....\................\.....\testbench_arch.obj
............\....\....\................\testbench_arch.h
............\....\....\................\xsimtestbench_arch.cpp
............\....\....\sub00
............\....\....\.....\vhpl00.vho
............\....\....\.....\vhpl01.vho
............\....\....\.....\vhpl02.vho
............\....\....\.....\vhpl03.vho
............\....\....\.....\vhpl04.vho
............\....\....\.....\vhpl05.vho
............\....\....\.....\vhpl06.vho
............\....\....\.....\vhpl07.vho
............\....\....\.....\vhpl08.vho
............\....\....\.....\vhpl09.vho
............\automake.log
............\fa1_tbw.ant
............\fa1_tbw.tbw
............\fa1_tbw.vhw
............\fa1_tbw.xwv
............\fa1_tbw.xwv_bak
............\fa1_tbw_bencher.prj
............\fa2_tbw.ant
............\fa2_tbw.fdo
............\fa2_tbw.tbw
............\fa2_tbw.udo
............\fa2_tbw.vhw
............\fa2_tbw.xwv
............\fa2_tbw.xwv_bak
............\fa2_tbw_bencher.prj
............\fa_tbw.ano
............\fa_tbw.ant
............\fa_tbw.fdo
............\fa_tbw.isim_beh_exe
............\fa_tbw.isim_beh_log
............\fa_tbw.isim_beh_prj
............\fa_tbw.isim_gen_exe
............\fa_tbw.isim_gen_prj
............\fa_tbw.jhd
............\fa_tbw.tbw
............\fa_tbw.udo
............\fa_tbw.vhw
............\fa_tbw.xwv
............\fa_tbw.xwv_bak
............\fa_tbw_beh.prj
............\fa_tbw_bencher.prj
............\fa_tbw_gen.prj
............\fa_tbw_isim_beh.exe
............\fa_tbw_tbxr.exe
............\fa_v.cmd_log
............\fa_v.lso
............\fa_v.ngc
............\fa_v.ngr
............\fa_v.prj
............\fa_v.spl
............\fa_v.stx
............\fa_v.sym
............\fa_v.syr
............\fa_v.vhd
............\fa_v_summary.html
............\isim
............\....\work
............\....\....\fa_tbw
............\....\....\......\entity.cpp
............\....\....\......\entity.h
............\....\....\......\mingw
............\....\....\......\.....\testbench_arch.obj
............\....\....\......\testbench_arch.h
............\....\....\......\xsimtestbench_arch.cpp
............\....\....\fa_v
............\....\....\....\behavioral.h
............\....\....\....\entity.cpp
............\....\....\....\entity.h
............\....\....\....\mingw
............\....\....\....\.....\behavioral.obj
............\....\....\hdllib.ref
............\....\....\hdpdeps.ref
............\....\....\rcv_tbw
............\....\....\.......\entity.cpp
............\....\....\.......\entity.h
............\....\....\.......\mingw
............\....\....\.......\.....\testbench_arch.obj
............\....\....\.......\testbench_arch.h
............\....\....\.......\xsimtestbench_arch.cpp
............\....\....\rcv_v
............\....\....\.....\behavioral.h
............\....\....\.....\entity.cpp
............\....\....\.....\entity.h
............\....\....\.....\mingw
............\....\....\.....\.....\behavioral.obj
............\....\....\sent_receive_sch
............\....\....\................\behavioral.h
............\....\....\................\entity.cpp
............\....\....\................\entity.h
............\....\....\................\mingw
............\....\....\................\.....\behavioral.obj
............\....\....\sent_receive_tbw
............\....\....\................\entity.cpp
............\....\....\................\entity.h
............\....\....\................\mingw
............\....\....\................\.....\testbench_arch.obj
............\....\....\................\testbench_arch.h
............\....\....\................\xsimtestbench_arch.cpp
............\....\....\sub00
............\....\....\.....\vhpl00.vho
............\....\....\.....\vhpl01.vho
............\....\....\.....\vhpl02.vho
............\....\....\.....\vhpl03.vho
............\....\....\.....\vhpl04.vho
............\....\....\.....\vhpl05.vho
............\....\....\.....\vhpl06.vho
............\....\....\.....\vhpl07.vho
............\....\....\.....\vhpl08.vho
............\....\....\.....\vhpl09.vho