文件名称:RISC_Core
介绍说明－－下载内容均来自于网络，请自行研究使用
这是用VerilogHDL描述的一个8位精简指令集处理器，包含完整代码，各种文档，以及测试环境。-This is described in VerilogHDL with an 8-bit RISC processor, including the integrity of the code, a variety of documents, as well as the test environment.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
RISC Core
.........\example_asm.txt
.........\risc8.pdf
.........\risc8_asm_pl.txt
.........\risc8_tar
.........\.........\risc8_tar
.........\verilog
.........\.......\bin
.........\.......\...\example.asm
.........\.......\...\example.hex
.........\.......\...\example.mem
.........\.......\...\risc8_asm.pl
.........\.......\doc
.........\.......\...\risc8.pdf
.........\.......\...\risc8.ps
.........\.......\sim
.........\.......\...\asm
.........\.......\...\...\and.asm
.........\.......\...\...\and.mem
.........\.......\...\...\arith.asm
.........\.......\...\...\arith.mem
.........\.......\...\...\assemble_all
.........\.......\...\...\divide.asm
.........\.......\...\...\divide.mem
.........\.......\...\...\flags.asm
.........\.......\...\...\flags.mem
.........\.......\...\...\interrupt.asm
.........\.......\...\...\interrupt.mem
.........\.......\...\...\jmp.asm
.........\.......\...\...\jmp.mem
.........\.......\...\...\loadstore.asm
.........\.......\...\...\loadstore.mem
.........\.......\...\...\logic.asm
.........\.......\...\...\logic.mem
.........\.......\...\...\moves.asm
.........\.......\...\...\moves.mem
.........\.......\...\...\multiply.asm
.........\.......\...\...\multiply.mem
.........\.......\...\...\or.asm
.........\.......\...\...\or.mem
.........\.......\...\...\staldapshpop.asm
.........\.......\...\...\staldapshpop.mem
.........\.......\...\...\waitstates.asm
.........\.......\...\...\waitstates.mem
.........\.......\...\compile
.........\.......\...\DW01_add.v
.........\.......\...\reg.mem
.........\.......\...\regression
.........\.......\...\risc8.cfg
.........\.......\...\run_batch
.........\.......\...\run_interac
.........\.......\...\test.mem
.........\.......\...\test.v
.........\.......\src
.........\.......\...\rbcla_adder.v
.........\.......\...\risc8.v
.........\.......\...\risc8_alu.v
.........\.......\...\risc8_constants.v
.........\.......\...\risc8_control.v
.........\.......\...\risc8_parameters.v
.........\.......\...\risc8_regb_biu.v
.........\.......\syn
.........\.......\...\risc8_dc_compile.scr
.........\example_asm.txt
.........\risc8.pdf
.........\risc8_asm_pl.txt
.........\risc8_tar
.........\.........\risc8_tar
.........\verilog
.........\.......\bin
.........\.......\...\example.asm
.........\.......\...\example.hex
.........\.......\...\example.mem
.........\.......\...\risc8_asm.pl
.........\.......\doc
.........\.......\...\risc8.pdf
.........\.......\...\risc8.ps
.........\.......\sim
.........\.......\...\asm
.........\.......\...\...\and.asm
.........\.......\...\...\and.mem
.........\.......\...\...\arith.asm
.........\.......\...\...\arith.mem
.........\.......\...\...\assemble_all
.........\.......\...\...\divide.asm
.........\.......\...\...\divide.mem
.........\.......\...\...\flags.asm
.........\.......\...\...\flags.mem
.........\.......\...\...\interrupt.asm
.........\.......\...\...\interrupt.mem
.........\.......\...\...\jmp.asm
.........\.......\...\...\jmp.mem
.........\.......\...\...\loadstore.asm
.........\.......\...\...\loadstore.mem
.........\.......\...\...\logic.asm
.........\.......\...\...\logic.mem
.........\.......\...\...\moves.asm
.........\.......\...\...\moves.mem
.........\.......\...\...\multiply.asm
.........\.......\...\...\multiply.mem
.........\.......\...\...\or.asm
.........\.......\...\...\or.mem
.........\.......\...\...\staldapshpop.asm
.........\.......\...\...\staldapshpop.mem
.........\.......\...\...\waitstates.asm
.........\.......\...\...\waitstates.mem
.........\.......\...\compile
.........\.......\...\DW01_add.v
.........\.......\...\reg.mem
.........\.......\...\regression
.........\.......\...\risc8.cfg
.........\.......\...\run_batch
.........\.......\...\run_interac
.........\.......\...\test.mem
.........\.......\...\test.v
.........\.......\src
.........\.......\...\rbcla_adder.v
.........\.......\...\risc8.v
.........\.......\...\risc8_alu.v
.........\.......\...\risc8_constants.v
.........\.......\...\risc8_control.v
.........\.......\...\risc8_parameters.v
.........\.......\...\risc8_regb_biu.v
.........\.......\syn
.........\.......\...\risc8_dc_compile.scr