压缩包 : 105230316pci.rar 列表
PCI\20061015192626944.rar
PCI\PCI _\FPGA提供的接口信号.pdf
PCI\PCI _\PCI卡驱动安装向导.pdf
PCI\PCI _\PCI卡文档.pdf
PCI\PCI _\天龙八步.pdf
PCI\PCI _\复件 说明.txt
PCI\PCI _\新建文件夹
PCI\PCI _
PCI\外包\外包要求.txt
PCI\外包
PCI\download.asp
PCI\download(1).asp
PCI\PLX_SDK_v5_10-Lite_Final_2007-06-29.exe
PCI\PCI开发板文档.rar
PCI\DESandRAM_FPGA.rar
PCI\DSlave----带中断VC.rar
PCI\FPGA程序--ram.rar
PCI\EP1C6Q240-8REG_WR.rar
PCI\PCIEEP.eep
PCI\PCI开发板文档\FPGA提供的接口信号.pdf
PCI\PCI开发板文档\PCI卡驱动安装向导.pdf
PCI\PCI开发板文档\PCI卡文档.pdf
PCI\PCI开发板文档\天龙八步.pdf
PCI\PCI开发板文档\FPGA内部部分程序，用户接口.jpg
PCI\PCI开发板文档\20061122121704mj.jpg
PCI\PCI开发板文档\说明.txt
PCI\PCI开发板文档
PCI\DESandRAM_FPGA\dd\PCI+DES\int\test.qws
PCI\DESandRAM_FPGA\dd\PCI+DES\int\test.bdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\test.qsf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\test.done
PCI\DESandRAM_FPGA\dd\PCI+DES\int\read.bsf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\ff_waveforms.html
PCI\DESandRAM_FPGA\dd\PCI+DES\int\ff_wave0.jpg
PCI\DESandRAM_FPGA\dd\PCI+DES\int\ff.vhd
PCI\DESandRAM_FPGA\dd\PCI+DES\int\ff.cmp
PCI\DESandRAM_FPGA\dd\PCI+DES\int\ff.bsf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\Rint.bsf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\Rint.vhd
PCI\DESandRAM_FPGA\dd\PCI+DES\int\int.bsf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\a.v
PCI\DESandRAM_FPGA\dd\PCI+DES\int\a.vhd
PCI\DESandRAM_FPGA\dd\PCI+DES\int\aa.v
PCI\DESandRAM_FPGA\dd\PCI+DES\int\test.map.summary
PCI\DESandRAM_FPGA\dd\PCI+DES\int\test.map.rpt
PCI\DESandRAM_FPGA\dd\PCI+DES\int\test.flow.rpt
PCI\DESandRAM_FPGA\dd\PCI+DES\int\test.sim.rpt
PCI\DESandRAM_FPGA\dd\PCI+DES\int\test.tan.rpt
PCI\DESandRAM_FPGA\dd\PCI+DES\int\test.sof
PCI\DESandRAM_FPGA\dd\PCI+DES\int\test.pof
PCI\DESandRAM_FPGA\dd\PCI+DES\int\test.asm.rpt
PCI\DESandRAM_FPGA\dd\PCI+DES\int\test.pin
PCI\DESandRAM_FPGA\dd\PCI+DES\int\test.fit.summary
PCI\DESandRAM_FPGA\dd\PCI+DES\int\test.fit.smsg
PCI\DESandRAM_FPGA\dd\PCI+DES\int\test.fit.rpt
PCI\DESandRAM_FPGA\dd\PCI+DES\int\read.vhd
PCI\DESandRAM_FPGA\dd\PCI+DES\int\interrupt.vhd
PCI\DESandRAM_FPGA\dd\PCI+DES\int\test.vhd
PCI\DESandRAM_FPGA\dd\PCI+DES\int\74138_0.vhd
PCI\DESandRAM_FPGA\dd\PCI+DES\int\test.tan.summary
PCI\DESandRAM_FPGA\dd\PCI+DES\int\test.vwf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\interrupt.bsf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\test.dpf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\test.tcl
PCI\DESandRAM_FPGA\dd\PCI+DES\int\tTRI.vhd
PCI\DESandRAM_FPGA\dd\PCI+DES\int\tTRI.cmp
PCI\DESandRAM_FPGA\dd\PCI+DES\int\tTRI.bsf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\test.cdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\test.qpf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\pllll_waveforms.html
PCI\DESandRAM_FPGA\dd\PCI+DES\int\pllll_wave0.jpg
PCI\DESandRAM_FPGA\dd\PCI+DES\int\pllll.ppf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\pllll.vhd
PCI\DESandRAM_FPGA\dd\PCI+DES\int\pllll.cmp
PCI\DESandRAM_FPGA\dd\PCI+DES\int\pllll.bsf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\cmp_state.ini
PCI\DESandRAM_FPGA\dd\PCI+DES\int\bt.vhd
PCI\DESandRAM_FPGA\dd\PCI+DES\int\bt.cmp
PCI\DESandRAM_FPGA\dd\PCI+DES\int\bt.bsf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\sim.cfg
PCI\DESandRAM_FPGA\dd\PCI+DES\int\ReadMailBox.bsf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\int.vhd
PCI\DESandRAM_FPGA\dd\PCI+DES\int\CLEAR.bsf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\test_assignment_defaults.qdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\CLEAR.vhd
PCI\DESandRAM_FPGA\dd\PCI+DES\int\write.vhd
PCI\DESandRAM_FPGA\dd\PCI+DES\int\write.bsf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\output_file.rbf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\output_file.ttf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\output_file.hexout
PCI\DESandRAM_FPGA\dd\PCI+DES\int\int.rar
PCI\DESandRAM_FPGA\dd\PCI+DES\int\read.vhd---
PCI\DESandRAM_FPGA\dd\PCI+DES\int\readfrompci.bsf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\R256.vwf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\ram256-.vhd
PCI\DESandRAM_FPGA\dd\PCI+DES\int\test1.bsf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\test1.vhd
PCI\DESandRAM_FPGA\dd\PCI+DES\int\ReadMailBox.vhd
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\cntr_vcc.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\cntr_ulb.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\wed.zsf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\cntr_vu7.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\mux_ngc.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\cmpr_fnh.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\cntr_0id.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\cntr_e0b.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\cmpr_33g.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\cntr_g08.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\cntr_tue.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\test_cmp.qrpt
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\mux_qp7.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\cntr_cha.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\cntr_708.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\test_sim.qrpt
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\cntr_0dc.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\cntr_e08.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dcfifo_pqb1.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\altsyncram_8941.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dcfifo_c751.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\cntr_su7.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\a_gray2bin_q4b.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\a_graycounter_j06.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\a_graycounter_k06.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\altsyncram_h3v.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\alt_synch_pipe_oc8.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dffpipe_id9.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\alt_synch_pipe_pc8.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dffpipe_jd9.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\add_sub_gub.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\cntr_808.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dcfifo_hd51.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\a_gray2bin_96b.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\a_graycounter_226.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\a_graycounter_326.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\altsyncram_f6v.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\cntr_vlb.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\cmpr_gnh.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\decode_tt6.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\alt_synch_pipe_7e8.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dffpipe_1f9.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\alt_synch_pipe_8e8.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dffpipe_2f9.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\add_sub_vvb.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dcfifo_9vb1.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\altsyncram_0c41.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\cntr_8id.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dcfifo_ap41.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\a_graycounter_l06.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\alt_synch_pipe_qc8.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dffpipe_kd9.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\alt_synch_pipe_rc8.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dffpipe_ld9.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dcfifo_1vb1.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dcfifo_bc51.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\a_gray2bin_86b.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\a_graycounter_126.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\a_graycounter_426.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\altsyncram_d6v.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\decode_ut6.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\mux_rp7.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\alt_synch_pipe_6e8.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dffpipe_0f9.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\alt_synch_pipe_9e8.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dffpipe_3f9.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\add_sub_uvb.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\cntr_d08.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\altsyncram_ub41.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dcfifo_t651.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dcfifo_ha51.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\a_gray2bin_46b.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\a_graycounter_t16.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\a_graycounter_u16.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\altsyncram_56v.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\alt_synch_pipe_2e8.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dffpipe_se9.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\alt_synch_pipe_3e8.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dffpipe_te9.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\add_sub_qvb.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\cntr_908.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\rom0_X_BOX_5ed6a4c_0.hdl.mif
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\rom1_X_BOX_5ed6a4c_0.hdl.mif
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\rom2_X_BOX_5ed6a4c_0.hdl.mif
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\rom3_X_BOX_5ed6a4c_0.hdl.mif
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\rom4_X_BOX_5ed6a4c_0.hdl.mif
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\rom5_X_BOX_5ed6a4c_0.hdl.mif
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\rom6_X_BOX_5ed6a4c_0.hdl.mif
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\rom7_X_BOX_5ed6a4c_0.hdl.mif
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\a_gray2bin_36b.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\a_graycounter_s16.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\a_graycounter_v16.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\altsyncram_36v.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\alt_synch_pipe_1e8.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dffpipe_re9.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\alt_synch_pipe_4e8.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dffpipe_ue9.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\add_sub_pvb.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\rom0_X_BOX_5ed6a4c.hdl.mif
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\rom1_X_BOX_5ed6a4c.hdl.mif
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\rom2_X_BOX_5ed6a4c.hdl.mif
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\rom3_X_BOX_5ed6a4c.hdl.mif
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\rom4_X_BOX_5ed6a4c.hdl.mif
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\rom5_X_BOX_5ed6a4c.hdl.mif
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\rom6_X_BOX_5ed6a4c.hdl.mif
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\rom7_X_BOX_5ed6a4c.hdl.mif
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\altsyncram_3nb2.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\cntr_ika.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\cntr_ubb.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\decode_9ie.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\altsyncram_brp2.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\decode_iga.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\mux_3eb.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\altsyncram_pmb2.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\cntr_eka.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\cntr_mbb.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\altsyncram_jqp2.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\decode_fga.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\mux_sdb.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dcfifo_u351.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\a_graycounter_m06.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\alt_synch_pipe_sc8.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dffpipe_md9.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\alt_synch_pipe_tc8.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dffpipe_nd9.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\altsyncram_tgb2.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dcfifo_d251.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\a_gray2bin_n4b.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dcfifo_l651.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\a_gray2bin_26b.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\a_graycounter_r16.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\a_graycounter_026.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\altsyncram_16v.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\alt_synch_pipe_0e8.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dffpipe_qe9.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\alt_synch_pipe_5e8.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dffpipe_ve9.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\add_sub_ovb.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\a_graycounter_g06.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\a_graycounter_h06.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\altsyncram_b3v.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\alt_synch_pipe_lc8.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dffpipe_fd9.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\alt_synch_pipe_mc8.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dffpipe_gd9.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\add_sub_dub.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dcfifo_sk61.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\a_graycounter_n06.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\alt_synch_pipe_vc8.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dffpipe_pd9.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\alt_synch_pipe_0d8.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dffpipe_qd9.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dcfifo_br51.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\a_graycounter_i06.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\alt_synch_pipe_nc8.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dffpipe_hd9.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\alt_synch_pipe_uc8.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\dffpipe_od9.tdf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\test.db_info
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\test.sld_design_entry.sci
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db\test.eco.cdb
PCI\DESandRAM_FPGA\dd\PCI+DES\int\db
PCI\DESandRAM_FPGA\dd\PCI+DES\int\test.map.eqn
PCI\DESandRAM_FPGA\dd\PCI+DES\int\test.fit.eqn
PCI\DESandRAM_FPGA\dd\PCI+DES\int\r.vwf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\Waveform1.vwf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\kk.vhd
PCI\DESandRAM_FPGA\dd\PCI+DES\int\kk.bsf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\PCI_SDR.bsf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\BIT32_BIT64.bsf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\DES_FINAL.bsf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\DES_PROCESS.bsf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\KEY_GEN.bsf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\X_BOX.bsf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\BIT64_BIT32.bsf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\readfrompci.vhd
PCI\DESandRAM_FPGA\dd\PCI+DES\int\stp1.stp
PCI\DESandRAM_FPGA\dd\PCI+DES\int\ramm.vhd
PCI\DESandRAM_FPGA\dd\PCI+DES\int\ram256.bsf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\t32.vhd
PCI\DESandRAM_FPGA\dd\PCI+DES\int\t32.cmp
PCI\DESandRAM_FPGA\dd\PCI+DES\int\t32.bsf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\PCI_SDR.v
PCI\DESandRAM_FPGA\dd\PCI+DES\int\ram256.vhd
PCI\DESandRAM_FPGA\dd\PCI+DES\int\or10.vhd
PCI\DESandRAM_FPGA\dd\PCI+DES\int\or10.cmp
PCI\DESandRAM_FPGA\dd\PCI+DES\int\or10.bsf
PCI\DESandRAM_FPGA\dd\PCI+DES\int\test.sdc
PCI\DESandRAM_FPGA\dd\PCI+DES\int
PCI\DESandRAM_FPGA\dd\PCI+DES
PCI\DESandRAM_FPGA\dd
PCI\DESandRAM_FPGA\ram256加上FLAGA.vhd
PCI\DESandRAM_FPGA
PCI\DSlave----带中断VC\DSlave----带中断VC\DSlave.c
PCI\DSlave----带中断VC\DSlave----带中断VC\data2.txt
PCI\DSlave----带中断VC\DSlave----带中断VC\mytest0.c
PCI\DSlave----带中断VC\DSlave----带中断VC\DSlave.dsw
PCI\DSlave----带中断VC\DSlave----带中断VC\DSlave.ncb
PCI\DSlave----带中断VC\DSlave----带中断VC\data.txt
PCI\DSlave----带中断VC\DSlave----带中断VC\data9.txt
PCI\DSlave----带中断VC\DSlave----带中断VC\mytest1.c
PCI\DSlave----带中断VC\DSlave----带中断VC\DSlave.plg
PCI\DSlave----带中断VC\DSlave----带中断VC\mytest.c
PCI\DSlave----带中断VC\DSlave----带中断VC\des.c
PCI\DSlave----带中断VC\DSlave----带中断VC\des.h
PCI\DSlave----带中断VC\DSlave----带中断VC\olddata1.txt
PCI\DSlave----带中断VC\DSlave----带中断VC\DSlave.dsp
PCI\DSlave----带中断VC\DSlave----带中断VC\olddata2.txt
PCI\DSlave----带中断VC\DSlave----带中断VC\Release
PCI\DSlave----带中断VC\DSlave----带中断VC\Debug
PCI\DSlave----带中断VC\DSlave----带中断VC\DSlave.opt
PCI\DSlave----带中断VC\DSlave----带中断VC
PCI\DSlave----带中断VC
PCI\FPGA程序--ram\nodestest\ram256加上FLAGA.vhd
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\test.qws
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\test.bdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\test.qsf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\test.done
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\read.bsf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\ff_waveforms.html
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\ff_wave0.jpg
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\ff.vhd
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\ff.cmp
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\ff.bsf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\Rint.bsf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\Rint.vhd
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\int.bsf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\a.v
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\a.vhd
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\aa.v
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\test.map.summary
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\test.map.rpt
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\test.flow.rpt
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\test.sim.rpt
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\test.tan.rpt
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\test.sof
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\test.pof
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\test.asm.rpt
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\test.pin
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\test.fit.summary
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\test.fit.smsg
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\test.fit.rpt
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\read.vhd
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\interrupt.vhd
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\test.vhd
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\74138_0.vhd
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\test.tan.summary
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\test.vwf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\interrupt.bsf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\test.dpf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\test.tcl
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\tTRI.vhd
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\tTRI.cmp
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\tTRI.bsf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\test.cdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\test.qpf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\pllll_waveforms.html
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\pllll_wave0.jpg
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\pllll.ppf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\pllll.vhd
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\pllll.cmp
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\pllll.bsf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\cmp_state.ini
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\bt.vhd
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\bt.cmp
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\bt.bsf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\sim.cfg
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\ReadMailBox.bsf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\int.vhd
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\CLEAR.bsf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\test_assignment_defaults.qdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\CLEAR.vhd
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\write.vhd
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\write.bsf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\output_file.rbf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\output_file.ttf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\output_file.hexout
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\int.rar
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\read.vhd---
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\readfrompci.bsf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\R256.vwf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\ram256-.vhd
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\test1.bsf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\test1.vhd
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\ReadMailBox.vhd
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\test.map.eqn
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\test.fit.eqn
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\r.vwf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\Waveform1.vwf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\kk.vhd
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\kk.bsf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\PCI_SDR.bsf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\BIT32_BIT64.bsf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\DES_FINAL.bsf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\DES_PROCESS.bsf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\KEY_GEN.bsf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\X_BOX.bsf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\BIT64_BIT32.bsf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\readfrompci.vhd
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\stp1.stp
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\ramm.vhd
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\ram256.bsf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\t32.vhd
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\t32.cmp
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\t32.bsf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\PCI_SDR.v
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\ram256.vhd
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\or10.vhd
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\or10.cmp
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\or10.bsf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\test.sdc
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\cntr_vcc.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\cntr_ulb.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\wed.zsf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\cntr_vu7.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\mux_ngc.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\cmpr_fnh.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\cntr_0id.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\cntr_e0b.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\cmpr_33g.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\cntr_g08.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\cntr_tue.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\test_cmp.qrpt
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\mux_qp7.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\cntr_cha.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\cntr_708.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\test_sim.qrpt
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\cntr_0dc.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\cntr_e08.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dcfifo_pqb1.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\altsyncram_8941.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dcfifo_c751.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\cntr_su7.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\a_gray2bin_q4b.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\a_graycounter_j06.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\a_graycounter_k06.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\altsyncram_h3v.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\alt_synch_pipe_oc8.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dffpipe_id9.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\alt_synch_pipe_pc8.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dffpipe_jd9.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\add_sub_gub.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\cntr_808.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dcfifo_hd51.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\a_gray2bin_96b.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\a_graycounter_226.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\a_graycounter_326.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\altsyncram_f6v.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\cntr_vlb.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\cmpr_gnh.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\decode_tt6.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\alt_synch_pipe_7e8.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dffpipe_1f9.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\alt_synch_pipe_8e8.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dffpipe_2f9.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\add_sub_vvb.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dcfifo_9vb1.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\altsyncram_0c41.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\cntr_8id.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dcfifo_ap41.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\a_graycounter_l06.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\alt_synch_pipe_qc8.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dffpipe_kd9.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\alt_synch_pipe_rc8.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dffpipe_ld9.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dcfifo_1vb1.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dcfifo_bc51.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\a_gray2bin_86b.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\a_graycounter_126.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\a_graycounter_426.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\altsyncram_d6v.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\decode_ut6.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\mux_rp7.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\alt_synch_pipe_6e8.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dffpipe_0f9.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\alt_synch_pipe_9e8.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dffpipe_3f9.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\add_sub_uvb.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\cntr_d08.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\altsyncram_ub41.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dcfifo_t651.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dcfifo_ha51.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\a_gray2bin_46b.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\a_graycounter_t16.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\a_graycounter_u16.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\altsyncram_56v.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\alt_synch_pipe_2e8.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dffpipe_se9.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\alt_synch_pipe_3e8.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dffpipe_te9.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\add_sub_qvb.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\cntr_908.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\rom0_X_BOX_5ed6a4c_0.hdl.mif
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\rom1_X_BOX_5ed6a4c_0.hdl.mif
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\rom2_X_BOX_5ed6a4c_0.hdl.mif
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\rom3_X_BOX_5ed6a4c_0.hdl.mif
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\rom4_X_BOX_5ed6a4c_0.hdl.mif
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\rom5_X_BOX_5ed6a4c_0.hdl.mif
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\rom6_X_BOX_5ed6a4c_0.hdl.mif
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\rom7_X_BOX_5ed6a4c_0.hdl.mif
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\a_gray2bin_36b.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\a_graycounter_s16.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\a_graycounter_v16.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\altsyncram_36v.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\alt_synch_pipe_1e8.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dffpipe_re9.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\alt_synch_pipe_4e8.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dffpipe_ue9.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\add_sub_pvb.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\rom0_X_BOX_5ed6a4c.hdl.mif
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\rom1_X_BOX_5ed6a4c.hdl.mif
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\rom2_X_BOX_5ed6a4c.hdl.mif
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\rom3_X_BOX_5ed6a4c.hdl.mif
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\rom4_X_BOX_5ed6a4c.hdl.mif
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\rom5_X_BOX_5ed6a4c.hdl.mif
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\rom6_X_BOX_5ed6a4c.hdl.mif
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\rom7_X_BOX_5ed6a4c.hdl.mif
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\altsyncram_3nb2.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\cntr_ika.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\cntr_ubb.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\decode_9ie.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\altsyncram_brp2.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\decode_iga.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\mux_3eb.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\altsyncram_pmb2.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\cntr_eka.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\cntr_mbb.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\altsyncram_jqp2.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\decode_fga.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\mux_sdb.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dcfifo_u351.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\a_graycounter_m06.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\alt_synch_pipe_sc8.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dffpipe_md9.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\alt_synch_pipe_tc8.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dffpipe_nd9.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\altsyncram_tgb2.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dcfifo_d251.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\a_gray2bin_n4b.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dcfifo_l651.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\a_gray2bin_26b.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\a_graycounter_r16.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\a_graycounter_026.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\altsyncram_16v.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\alt_synch_pipe_0e8.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dffpipe_qe9.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\alt_synch_pipe_5e8.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dffpipe_ve9.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\add_sub_ovb.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\a_graycounter_g06.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\a_graycounter_h06.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\altsyncram_b3v.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\alt_synch_pipe_lc8.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dffpipe_fd9.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\alt_synch_pipe_mc8.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dffpipe_gd9.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\add_sub_dub.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dcfifo_sk61.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\a_graycounter_n06.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\alt_synch_pipe_vc8.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dffpipe_pd9.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\alt_synch_pipe_0d8.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dffpipe_qd9.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dcfifo_br51.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\a_graycounter_i06.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\alt_synch_pipe_nc8.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dffpipe_hd9.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\alt_synch_pipe_uc8.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dffpipe_od9.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\dcfifo_4p61.tdf
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\test.db_info
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\test.sld_design_entry.sci
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db\test.eco.cdb
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int\db
PCI\FPGA程序--ram\nodestest\dd\PCI+DES\int
PCI\FPGA程序--ram\nodestest\dd\PCI+DES
PCI\FPGA程序--ram\nodestest\dd
PCI\FPGA程序--ram\nodestest
PCI\FPGA程序--ram
PCI\EP1C6Q240-8REG_WR\reg_wr\write.vhd
PCI\EP1C6Q240-8REG_WR\reg_wr\test.qws
PCI\EP1C6Q240-8REG_WR\reg_wr\test.bdf
PCI\EP1C6Q240-8REG_WR\reg_wr\test.done
PCI\EP1C6Q240-8REG_WR\reg_wr\read.bsf
PCI\EP1C6Q240-8REG_WR\reg_wr\read.vhd
PCI\EP1C6Q240-8REG_WR\reg_wr\ff_waveforms.html
PCI\EP1C6Q240-8REG_WR\reg_wr\ff_wave0.jpg
PCI\EP1C6Q240-8REG_WR\reg_wr\ff.vhd
PCI\EP1C6Q240-8REG_WR\reg_wr\ff.cmp
PCI\EP1C6Q240-8REG_WR\reg_wr\ff.bsf
PCI\EP1C6Q240-8REG_WR\reg_wr\Rint.bsf
PCI\EP1C6Q240-8REG_WR\reg_wr\Rint.vhd
PCI\EP1C6Q240-8REG_WR\reg_wr\int.bsf
PCI\EP1C6Q240-8REG_WR\reg_wr\a.v
PCI\EP1C6Q240-8REG_WR\reg_wr\a.vhd
PCI\EP1C6Q240-8REG_WR\reg_wr\aa.v
PCI\EP1C6Q240-8REG_WR\reg_wr\test.map.summary
PCI\EP1C6Q240-8REG_WR\reg_wr\test.map.rpt
PCI\EP1C6Q240-8REG_WR\reg_wr\test.flow.rpt
PCI\EP1C6Q240-8REG_WR\reg_wr\test.sim.rpt
PCI\EP1C6Q240-8REG_WR\reg_wr\test.tan.rpt
PCI\EP1C6Q240-8REG_WR\reg_wr\test.sof
PCI\EP1C6Q240-8REG_WR\reg_wr\test.pof
PCI\EP1C6Q240-8REG_WR\reg_wr\test.asm.rpt
PCI\EP1C6Q240-8REG_WR\reg_wr\test.pin
PCI\EP1C6Q240-8REG_WR\reg_wr\test.fit.summary
PCI\EP1C6Q240-8REG_WR\reg_wr\test.fit.smsg
PCI\EP1C6Q240-8REG_WR\reg_wr\test.fit.rpt
PCI\EP1C6Q240-8REG_WR\reg_wr\Waveform1.vwf
PCI\EP1C6Q240-8REG_WR\reg_wr\interrupt.vhd
PCI\EP1C6Q240-8REG_WR\reg_wr\test.vhd
PCI\EP1C6Q240-8REG_WR\reg_wr\74138_0.vhd
PCI\EP1C6Q240-8REG_WR\reg_wr\test.tan.summary
PCI\EP1C6Q240-8REG_WR\reg_wr\test.vwf
PCI\EP1C6Q240-8REG_WR\reg_wr\interrupt.bsf
PCI\EP1C6Q240-8REG_WR\reg_wr\test.dpf
PCI\EP1C6Q240-8REG_WR\reg_wr\test.tcl
PCI\EP1C6Q240-8REG_WR\reg_wr\tTRI.vhd
PCI\EP1C6Q240-8REG_WR\reg_wr\tTRI.cmp
PCI\EP1C6Q240-8REG_WR\reg_wr\tTRI.bsf
PCI\EP1C6Q240-8REG_WR\reg_wr\test.cdf
PCI\EP1C6Q240-8REG_WR\reg_wr\test.qpf
PCI\EP1C6Q240-8REG_WR\reg_wr\pllll_waveforms.html
PCI\EP1C6Q240-8REG_WR\reg_wr\pllll_wave0.jpg
PCI\EP1C6Q240-8REG_WR\reg_wr\pllll.ppf
PCI\EP1C6Q240-8REG_WR\reg_wr\pllll.vhd
PCI\EP1C6Q240-8REG_WR\reg_wr\pllll.cmp
PCI\EP1C6Q240-8REG_WR\reg_wr\pllll.bsf
PCI\EP1C6Q240-8REG_WR\reg_wr\cmp_state.ini
PCI\EP1C6Q240-8REG_WR\reg_wr\bt.vhd
PCI\EP1C6Q240-8REG_WR\reg_wr\bt.cmp
PCI\EP1C6Q240-8REG_WR\reg_wr\bt.bsf
PCI\EP1C6Q240-8REG_WR\reg_wr\sim.cfg
PCI\EP1C6Q240-8REG_WR\reg_wr\test_assignment_defaults.qdf
PCI\EP1C6Q240-8REG_WR\reg_wr\test.qsf.bak
PCI\EP1C6Q240-8REG_WR\reg_wr\test.qsf
PCI\EP1C6Q240-8REG_WR\reg_wr\test.map.eqn
PCI\EP1C6Q240-8REG_WR\reg_wr\test.fit.eqn
PCI\EP1C6Q240-8REG_WR\reg_wr\test.fld
PCI\EP1C6Q240-8REG_WR\reg_wr\int.vhd.bak
PCI\EP1C6Q240-8REG_WR\reg_wr\int.vhd
PCI\EP1C6Q240-8REG_WR\reg_wr\_desktop.ini
PCI\EP1C6Q240-8REG_WR\reg_wr\db\wed.zsf
PCI\EP1C6Q240-8REG_WR\reg_wr\db\test_cmp.qrpt
PCI\EP1C6Q240-8REG_WR\reg_wr\db\test_sim.qrpt
PCI\EP1C6Q240-8REG_WR\reg_wr\db\_desktop.ini
PCI\EP1C6Q240-8REG_WR\reg_wr\db\test.db_info
PCI\EP1C6Q240-8REG_WR\reg_wr\db\test.sld_design_entry.sci
PCI\EP1C6Q240-8REG_WR\reg_wr\db\test.eco.cdb
PCI\EP1C6Q240-8REG_WR\reg_wr\db
PCI\EP1C6Q240-8REG_WR\reg_wr
PCI\EP1C6Q240-8REG_WR
PCI\PCI.exe
PCI\DSlave--单步调试VC.rar
PCI\DSlave--单步调试VC\DSlave--单步调试VC\DSlave.c
PCI\DSlave--单步调试VC\DSlave--单步调试VC\DSlave.dsw
PCI\DSlave--单步调试VC\DSlave--单步调试VC\DSlave.ncb
PCI\DSlave--单步调试VC\DSlave--单步调试VC\DSlave.plg
PCI\DSlave--单步调试VC\DSlave--单步调试VC\mytest.c
PCI\DSlave--单步调试VC\DSlave--单步调试VC\DSlave.dsp
PCI\DSlave--单步调试VC\DSlave--单步调试VC\Release
PCI\DSlave--单步调试VC\DSlave--单步调试VC\Debug
PCI\DSlave--单步调试VC\DSlave--单步调试VC\DSlave.opt
PCI\DSlave--单步调试VC\DSlave--单步调试VC
PCI\DSlave--单步调试VC
PCI