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压缩包 : 77433629an502_design_example.zip 列表 SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/ SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/code/ SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/code/arbitration.v SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/code/bus_idle_detect.v SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/code/mod__crc.v SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/code/op_stage.v SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/code/oscillator.v SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/code/smbus_controller.v SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/ SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/arbitration.v SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/bus_idle_detect.v SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/mod__crc.v SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/op_stage.v SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/oscillator.v SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/smbus_controller.cr.mti SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/smbus_controller.mpf SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/smbus_controller.v SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/transcript SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/tst_bnch.v SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/vsim.wlf SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/wave.bmp SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/wave.do SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/ SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/arbitration/ SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/arbitration/verilog.psm SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/arbitration/_primary.dat SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/arbitration/_primary.vhd SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/bus_idle_detect/ SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/bus_idle_detect/verilog.psm SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/bus_idle_detect/_primary.dat SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/bus_idle_detect/_primary.vhd SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/clkgen_low_extend_detect/ SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/clkgen_low_extend_detect/verilog.psm SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/clkgen_low_extend_detect/_primary.dat SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/clkgen_low_extend_detect/_primary.vhd SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/fsm/ SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/fsm/verilog.psm SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/fsm/_primary.dat SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/fsm/_primary.vhd SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/mod_crc/ SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/mod_crc/verilog.psm SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/mod_crc/_primary.dat SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/mod_crc/_primary.vhd SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/oscillator/ SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/oscillator/verilog.psm SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/oscillator/_primary.dat SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/oscillator/_primary.vhd SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/oscillator_altufm_osc_7p3/ SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/oscillator_altufm_osc_7p3/verilog.psm SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/oscillator_altufm_osc_7p3/_primary.dat SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/oscillator_altufm_osc_7p3/_primary.vhd SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/output_stage/ SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/output_stage/verilog.psm SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/output_stage/_primary.dat SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/output_stage/_primary.vhd SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/pec/ SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/pec/verilog.psm SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/pec/_primary.dat SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/pec/_primary.vhd SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/piso/ SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/piso/verilog.psm SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/piso/_primary.dat SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/piso/_primary.vhd SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/smbus_controller/ SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/smbus_controller/verilog.psm SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/smbus_controller/_primary.dat SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/smbus_controller/_primary.vhd SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/test_bench/ SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/test_bench/verilog.psm SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/test_bench/_primary.dat SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/test_bench/_primary.vhd SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/_info SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/ SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/arbitration.v SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/bus_idle_detect.v SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/ SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.(0).cnf.cdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.(0).cnf.hdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.(1).cnf.cdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.(1).cnf.hdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.(2).cnf.cdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.(2).cnf.hdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.(3).cnf.cdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.(3).cnf.hdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.(4).cnf.cdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.(4).cnf.hdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.(5).cnf.cdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.(5).cnf.hdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.(6).cnf.cdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.(6).cnf.hdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.(7).cnf.cdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.(7).cnf.hdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.(8).cnf.cdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.(8).cnf.hdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.(9).cnf.cdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.(9).cnf.hdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.asm.qmsg SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.asm_labs.ddb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.cbx.xml SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.cmp.cdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.cmp.hdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.cmp.logdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.cmp.rdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.cmp.tdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.cmp0.ddb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.dbp SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.db_info SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.eco.cdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.fit.qmsg SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.hier_info SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.hif SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.map.cdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.map.hdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.map.logdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.map.qmsg SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.pre_map.cdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.pre_map.hdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.psp SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.pss SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.rtlv.hdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.rtlv_sg.cdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.rtlv_sg_swap.cdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.sgdiff.cdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.sgdiff.hdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.signalprobe.cdb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.sld_design_entry.sci SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.sld_design_entry_dsc.sci SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.smp_dump.txt SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.syn_hier_info SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.tan.qmsg SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.tis_db_list.ddb SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/mod__crc.v SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/op_stage.v SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/oscillator.v SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/smbus_controller.asm.rpt SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/smbus_controller.done SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/smbus_controller.dpf SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/smbus_controller.fit.rpt SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/smbus_controller.fit.smsg SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/smbus_controller.fit.summary SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/smbus_controller.flow.rpt SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/smbus_controller.map.rpt SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/smbus_controller.map.smsg SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/smbus_controller.map.summary SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/smbus_controller.pin SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/smbus_controller.pof SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/smbus_controller.qpf SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/smbus_controller.qsf SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/smbus_controller.qws SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/smbus_controller.tan.rpt SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/smbus_controller.tan.summary SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/smbus_controller.v SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/smbus_controller_assignment_defaults.qdf SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/testbench/ SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/testbench/tst_bnch.v