文件名称:SDRAM控制核
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SDRAM控制核SDRAM控制核
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压缩包 : SDRAM_Altera_MAX_II_CPLD_Design_Example.rar 列表 Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\code\addr_gen.v Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\code\mobile_sdram.v Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\code\upcount_2.v Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\code\upcount_4.v Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\addr_gen.v Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\mobile_sdram.cr.mti Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\mobile_sdram.mpf Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\mobile_sdram.v Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\test_mob_sdram.v Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\upcount_2.v Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\upcount_4.v Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\vsim.wlf Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\wave.bmp Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\wave.do Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\addr_gen\verilog.psm Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\addr_gen\_primary.dat Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\addr_gen\_primary.vhd Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\mobile_sdram\verilog.psm Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\mobile_sdram\_primary.dat Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\mobile_sdram\_primary.vhd Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\test_mob_sdram\verilog.psm Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\test_mob_sdram\_primary.dat Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\test_mob_sdram\_primary.vhd Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\upcount_2\verilog.psm Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\upcount_2\_primary.dat Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\upcount_2\_primary.vhd Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\upcount_4\verilog.psm Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\upcount_4\_primary.dat Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\upcount_4\_primary.vhd Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\_info Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\quartus\addr_gen.v Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\quartus\db\mobile_sdram.db_info Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\quartus\db\mobile_sdram.sld_design_entry.sci Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\quartus\db\mobile_sdram.eco.cdb Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\quartus\mobile_sdram.asm.rpt Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\quartus\mobile_sdram.done Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\quartus\mobile_sdram.fit.rpt Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\quartus\mobile_sdram.fit.smsg Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\quartus\mobile_sdram.fit.summary Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\quartus\mobile_sdram.flow.rpt Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\quartus\mobile_sdram.map.rpt Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\quartus\mobile_sdram.map.summary Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\quartus\mobile_sdram.pin Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\quartus\mobile_sdram.pof Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\quartus\mobile_sdram.qpf Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\quartus\mobile_sdram.qsf Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\quartus\mobile_sdram.tan.rpt Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\quartus\mobile_sdram.tan.summary Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\quartus\mobile_sdram.v Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\quartus\mobile_sdram_assignment_defaults.qdf Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\quartus\upcount_2.v Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\quartus\upcount_4.v Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\quartus\mobile_sdram.qws Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\testbench\test_mob_sdram.v Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\addr_gen Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\mobile_sdram Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\test_mob_sdram Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\upcount_2 Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\upcount_4 Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\quartus\db Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\code Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\quartus Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\testbench Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example