有实验结果,用MOSIN6编写的,是Verilog HDL语言实现的.

练习三 利用条件语句实现计数分频时序电路

实验目的：

1.　　掌握条件语句在简单时序模块设计中的使用；

2.　　学习在Verilog模块中应用计数器；

3.　　学习测试模块的编写、综合和不同层次的仿真。

练习四 阻塞赋值与非阻塞赋值的区别

实验目的：

1．　　通过实验，掌握阻塞赋值与非阻塞赋值的概念和区别；

2．　　了解阻塞赋值与非阻塞赋值的不同使用场合；

3．　　学习测试模块的编写、综合和不同层次的仿真。

-The experimental results are used to prepare MOSIN6 is achieved Verilog HDL language. Practice the use of conditional statements to achieve the three sub-frequency timing circuit count experimental purposes: 1. Have conditional statements in the simple timing of the use of modular design　2. Learning modules in the Verilog Application of counter　3. to learn the preparation of the test module, integrated and different levels of simulation. Practicing the four blocking assignment with the distinction between non-blocking assignment experimental purposes: 1. Through experiments, hands blocking assignment with the concept of non-blocking assignment and distinction　2. Understanding of blocking and nonblocking assignment assignment using different occasions　3. Test the preparation of learning modules, integrated and different levels of simulation.