压缩包 : 15883869mi2c.rar 列表
mi2c\docs\docs.readme
mi2c\docs\mi2c_pd.pdf
mi2c\docs\mi2c_ps.pdf
mi2c\docs
mi2c\mi2c.readme
mi2c\verilog\gate_sim\comp_altera_lib.do
mi2c\verilog\gate_sim\comp_gate.do
mi2c\verilog\gate_sim\gate_sim.readme
mi2c\verilog\gate_sim\mi2c_tb.bat
mi2c\verilog\gate_sim\mi2c_tb.do
mi2c\verilog\gate_sim\mi2c_tb.ref
mi2c\verilog\gate_sim\mi2c_tb.scr
mi2c\verilog\gate_sim\mi2c_tb_diff.bat
mi2c\verilog\gate_sim\mi2c_tb_diff.scr
mi2c\verilog\gate_sim\work\mi2c_tb\verilog.asm
mi2c\verilog\gate_sim\work\mi2c_tb\_primary.dat
mi2c\verilog\gate_sim\work\mi2c_tb\_primary.vhd
mi2c\verilog\gate_sim\work\mi2c_tb
mi2c\verilog\gate_sim\work\_info
mi2c\verilog\gate_sim\work
mi2c\verilog\gate_sim
mi2c\verilog\rtl_encrypted\m3s001br.v
mi2c\verilog\rtl_encrypted\m3s001br.v.old
mi2c\verilog\rtl_encrypted\m3s002br.v
mi2c\verilog\rtl_encrypted\m3s002br.v.old
mi2c\verilog\rtl_encrypted\m3s003br.v
mi2c\verilog\rtl_encrypted\m3s003br.v.old
mi2c\verilog\rtl_encrypted\m3s004br.v
mi2c\verilog\rtl_encrypted\m3s004br.v.old
mi2c\verilog\rtl_encrypted\m3s005br.v
mi2c\verilog\rtl_encrypted\m3s005br.v.old
mi2c\verilog\rtl_encrypted\m3s006br.v
mi2c\verilog\rtl_encrypted\m3s006br.v.old
mi2c\verilog\rtl_encrypted\m3s007br.v
mi2c\verilog\rtl_encrypted\m3s007br.v.old
mi2c\verilog\rtl_encrypted\m3s008br.v
mi2c\verilog\rtl_encrypted\m3s008br.v.old
mi2c\verilog\rtl_encrypted\m3s009br.v
mi2c\verilog\rtl_encrypted\m3s009br.v.old
mi2c\verilog\rtl_encrypted\m3s010br.v
mi2c\verilog\rtl_encrypted\m3s010br.v.old
mi2c\verilog\rtl_encrypted\m3s011br.v
mi2c\verilog\rtl_encrypted\m3s011br.v.old
mi2c\verilog\rtl_encrypted\mi2c.v
mi2c\verilog\rtl_encrypted\mi2c.v.old
mi2c\verilog\rtl_encrypted\rtl_encrypted.readme
mi2c\verilog\rtl_encrypted
mi2c\verilog\rtl_sim\mi2c_tb.bat
mi2c\verilog\rtl_sim\mi2c_tb.do
mi2c\verilog\rtl_sim\mi2c_tb.ref
mi2c\verilog\rtl_sim\mi2c_tb.scr
mi2c\verilog\rtl_sim\mi2c_tb_diff.bat
mi2c\verilog\rtl_sim\mi2c_tb_diff.scr
mi2c\verilog\rtl_sim\rtl_sim.readme
mi2c\verilog\rtl_sim\work\m3s001br\verilog.asm
mi2c\verilog\rtl_sim\work\m3s001br\_primary.dat
mi2c\verilog\rtl_sim\work\m3s001br\_primary.vhd
mi2c\verilog\rtl_sim\work\m3s001br
mi2c\verilog\rtl_sim\work\m3s002br\verilog.asm
mi2c\verilog\rtl_sim\work\m3s002br\_primary.dat
mi2c\verilog\rtl_sim\work\m3s002br\_primary.vhd
mi2c\verilog\rtl_sim\work\m3s002br
mi2c\verilog\rtl_sim\work\m3s003br\verilog.asm
mi2c\verilog\rtl_sim\work\m3s003br\_primary.dat
mi2c\verilog\rtl_sim\work\m3s003br\_primary.vhd
mi2c\verilog\rtl_sim\work\m3s003br
mi2c\verilog\rtl_sim\work\m3s004br\verilog.asm
mi2c\verilog\rtl_sim\work\m3s004br\_primary.dat
mi2c\verilog\rtl_sim\work\m3s004br\_primary.vhd
mi2c\verilog\rtl_sim\work\m3s004br
mi2c\verilog\rtl_sim\work\m3s005br\verilog.asm
mi2c\verilog\rtl_sim\work\m3s005br\_primary.dat
mi2c\verilog\rtl_sim\work\m3s005br\_primary.vhd
mi2c\verilog\rtl_sim\work\m3s005br
mi2c\verilog\rtl_sim\work\m3s006br\verilog.asm
mi2c\verilog\rtl_sim\work\m3s006br\_primary.dat
mi2c\verilog\rtl_sim\work\m3s006br\_primary.vhd
mi2c\verilog\rtl_sim\work\m3s006br
mi2c\verilog\rtl_sim\work\m3s007br\verilog.asm
mi2c\verilog\rtl_sim\work\m3s007br\_primary.dat
mi2c\verilog\rtl_sim\work\m3s007br\_primary.vhd
mi2c\verilog\rtl_sim\work\m3s007br
mi2c\verilog\rtl_sim\work\m3s008br\verilog.asm
mi2c\verilog\rtl_sim\work\m3s008br\_primary.dat
mi2c\verilog\rtl_sim\work\m3s008br\_primary.vhd
mi2c\verilog\rtl_sim\work\m3s008br
mi2c\verilog\rtl_sim\work\m3s009br\verilog.asm
mi2c\verilog\rtl_sim\work\m3s009br\_primary.dat
mi2c\verilog\rtl_sim\work\m3s009br\_primary.vhd
mi2c\verilog\rtl_sim\work\m3s009br
mi2c\verilog\rtl_sim\work\m3s010br\verilog.asm
mi2c\verilog\rtl_sim\work\m3s010br\_primary.dat
mi2c\verilog\rtl_sim\work\m3s010br\_primary.vhd
mi2c\verilog\rtl_sim\work\m3s010br
mi2c\verilog\rtl_sim\work\m3s011br\verilog.asm
mi2c\verilog\rtl_sim\work\m3s011br\_primary.dat
mi2c\verilog\rtl_sim\work\m3s011br\_primary.vhd
mi2c\verilog\rtl_sim\work\m3s011br
mi2c\verilog\rtl_sim\work\mi2c\verilog.asm
mi2c\verilog\rtl_sim\work\mi2c\_primary.dat
mi2c\verilog\rtl_sim\work\mi2c\_primary.vhd
mi2c\verilog\rtl_sim\work\mi2c
mi2c\verilog\rtl_sim\work\mi2c_tb\verilog.asm
mi2c\verilog\rtl_sim\work\mi2c_tb\_primary.dat
mi2c\verilog\rtl_sim\work\mi2c_tb\_primary.vhd
mi2c\verilog\rtl_sim\work\mi2c_tb
mi2c\verilog\rtl_sim\work\_info
mi2c\verilog\rtl_sim\work
mi2c\verilog\rtl_sim
mi2c\verilog\synth\do_ip.tcl
mi2c\verilog\synth\quartus\quartus.bat
mi2c\verilog\synth\quartus\quartus.readme
mi2c\verilog\synth\quartus\quartus.scr
mi2c\verilog\synth\quartus\quartus.tcl
mi2c\verilog\synth\quartus
mi2c\verilog\synth\setup.tcl
mi2c\verilog\synth\spectrum.bat
mi2c\verilog\synth\spectrum.scr
mi2c\verilog\synth\spectrum.tcl
mi2c\verilog\synth\synth.readme
mi2c\verilog\synth
mi2c\verilog\template\mi2c.bsf
mi2c\verilog\template\mi2c.template
mi2c\verilog\template\template.readme
mi2c\verilog\template
mi2c\verilog\verilog.readme
mi2c\verilog
mi2c\vhdl\gate_sim\comp_altera_lib.do
mi2c\vhdl\gate_sim\comp_gate.do
mi2c\vhdl\gate_sim\gate_sim.readme
mi2c\vhdl\gate_sim\mi2c_tb.bat
mi2c\vhdl\gate_sim\mi2c_tb.do
mi2c\vhdl\gate_sim\mi2c_tb.ref
mi2c\vhdl\gate_sim\mi2c_tb.scr
mi2c\vhdl\gate_sim\mi2c_tb_diff.bat
mi2c\vhdl\gate_sim\mi2c_tb_diff.scr
mi2c\vhdl\gate_sim\work\mi2c_tb\behaviour.asm
mi2c\vhdl\gate_sim\work\mi2c_tb\behaviour.dat
mi2c\vhdl\gate_sim\work\mi2c_tb\_primary.dat
mi2c\vhdl\gate_sim\work\mi2c_tb
mi2c\vhdl\gate_sim\work\_info
mi2c\vhdl\gate_sim\work
mi2c\vhdl\gate_sim
mi2c\vhdl\rtl_encrypted\m3s001br.vhd
mi2c\vhdl\rtl_encrypted\m3s001br.vhd.old
mi2c\vhdl\rtl_encrypted\m3s002br.vhd
mi2c\vhdl\rtl_encrypted\m3s002br.vhd.old
mi2c\vhdl\rtl_encrypted\m3s003br.vhd
mi2c\vhdl\rtl_encrypted\m3s003br.vhd.old
mi2c\vhdl\rtl_encrypted\m3s004br.vhd
mi2c\vhdl\rtl_encrypted\m3s004br.vhd.old
mi2c\vhdl\rtl_encrypted\m3s005br.vhd
mi2c\vhdl\rtl_encrypted\m3s005br.vhd.old
mi2c\vhdl\rtl_encrypted\m3s006br.vhd
mi2c\vhdl\rtl_encrypted\m3s006br.vhd.old
mi2c\vhdl\rtl_encrypted\m3s007br.vhd
mi2c\vhdl\rtl_encrypted\m3s007br.vhd.old
mi2c\vhdl\rtl_encrypted\m3s008br.vhd
mi2c\vhdl\rtl_encrypted\m3s008br.vhd.old
mi2c\vhdl\rtl_encrypted\m3s009br.vhd
mi2c\vhdl\rtl_encrypted\m3s009br.vhd.old
mi2c\vhdl\rtl_encrypted\m3s010br.vhd
mi2c\vhdl\rtl_encrypted\m3s010br.vhd.old
mi2c\vhdl\rtl_encrypted\m3s011br.vhd
mi2c\vhdl\rtl_encrypted\m3s011br.vhd.old
mi2c\vhdl\rtl_encrypted\mi2c.vhd
mi2c\vhdl\rtl_encrypted\mi2c.vhd.old
mi2c\vhdl\rtl_encrypted\rtl_encrypted.readme
mi2c\vhdl\rtl_encrypted
mi2c\vhdl\rtl_sim\mi2c_tb.bat
mi2c\vhdl\rtl_sim\mi2c_tb.do
mi2c\vhdl\rtl_sim\mi2c_tb.ref
mi2c\vhdl\rtl_sim\mi2c_tb.scr
mi2c\vhdl\rtl_sim\mi2c_tb_diff.bat
mi2c\vhdl\rtl_sim\mi2c_tb_diff.scr
mi2c\vhdl\rtl_sim\rtl_sim.readme
mi2c\vhdl\rtl_sim\work\m3s001br\rtl.asm
mi2c\vhdl\rtl_sim\work\m3s001br\rtl.dat
mi2c\vhdl\rtl_sim\work\m3s001br\_primary.dat
mi2c\vhdl\rtl_sim\work\m3s001br
mi2c\vhdl\rtl_sim\work\m3s002br\rtl.asm
mi2c\vhdl\rtl_sim\work\m3s002br\rtl.dat
mi2c\vhdl\rtl_sim\work\m3s002br\_primary.dat
mi2c\vhdl\rtl_sim\work\m3s002br
mi2c\vhdl\rtl_sim\work\m3s003br\rtl.asm
mi2c\vhdl\rtl_sim\work\m3s003br\rtl.dat
mi2c\vhdl\rtl_sim\work\m3s003br\_primary.dat
mi2c\vhdl\rtl_sim\work\m3s003br
mi2c\vhdl\rtl_sim\work\m3s004br\rtl.asm
mi2c\vhdl\rtl_sim\work\m3s004br\rtl.dat
mi2c\vhdl\rtl_sim\work\m3s004br\_primary.dat
mi2c\vhdl\rtl_sim\work\m3s004br
mi2c\vhdl\rtl_sim\work\m3s005br\rtl.asm
mi2c\vhdl\rtl_sim\work\m3s005br\rtl.dat
mi2c\vhdl\rtl_sim\work\m3s005br\_primary.dat
mi2c\vhdl\rtl_sim\work\m3s005br
mi2c\vhdl\rtl_sim\work\m3s006br\rtl.asm
mi2c\vhdl\rtl_sim\work\m3s006br\rtl.dat
mi2c\vhdl\rtl_sim\work\m3s006br\_primary.dat
mi2c\vhdl\rtl_sim\work\m3s006br
mi2c\vhdl\rtl_sim\work\m3s007br\rtl.asm
mi2c\vhdl\rtl_sim\work\m3s007br\rtl.dat
mi2c\vhdl\rtl_sim\work\m3s007br\_primary.dat
mi2c\vhdl\rtl_sim\work\m3s007br
mi2c\vhdl\rtl_sim\work\m3s008br\rtl.asm
mi2c\vhdl\rtl_sim\work\m3s008br\rtl.dat
mi2c\vhdl\rtl_sim\work\m3s008br\_primary.dat
mi2c\vhdl\rtl_sim\work\m3s008br
mi2c\vhdl\rtl_sim\work\m3s009br\rtl.asm
mi2c\vhdl\rtl_sim\work\m3s009br\rtl.dat
mi2c\vhdl\rtl_sim\work\m3s009br\_primary.dat
mi2c\vhdl\rtl_sim\work\m3s009br
mi2c\vhdl\rtl_sim\work\m3s010br\rtl.asm
mi2c\vhdl\rtl_sim\work\m3s010br\rtl.dat
mi2c\vhdl\rtl_sim\work\m3s010br\_primary.dat
mi2c\vhdl\rtl_sim\work\m3s010br
mi2c\vhdl\rtl_sim\work\m3s011br\rtl.asm
mi2c\vhdl\rtl_sim\work\m3s011br\rtl.dat
mi2c\vhdl\rtl_sim\work\m3s011br\_primary.dat
mi2c\vhdl\rtl_sim\work\m3s011br
mi2c\vhdl\rtl_sim\work\mi2c\rtl.asm
mi2c\vhdl\rtl_sim\work\mi2c\rtl.dat
mi2c\vhdl\rtl_sim\work\mi2c\_primary.dat
mi2c\vhdl\rtl_sim\work\mi2c
mi2c\vhdl\rtl_sim\work\mi2c_tb\behaviour.asm
mi2c\vhdl\rtl_sim\work\mi2c_tb\behaviour.dat
mi2c\vhdl\rtl_sim\work\mi2c_tb\_primary.dat
mi2c\vhdl\rtl_sim\work\mi2c_tb
mi2c\vhdl\rtl_sim\work\_info
mi2c\vhdl\rtl_sim\work
mi2c\vhdl\rtl_sim
mi2c\vhdl\synth\do_ip.tcl
mi2c\vhdl\synth\quartus\quartus.bat
mi2c\vhdl\synth\quartus\quartus.readme
mi2c\vhdl\synth\quartus\quartus.scr
mi2c\vhdl\synth\quartus\quartus.tcl
mi2c\vhdl\synth\quartus
mi2c\vhdl\synth\setup.tcl
mi2c\vhdl\synth\spectrum.bat
mi2c\vhdl\synth\spectrum.scr
mi2c\vhdl\synth\spectrum.tcl
mi2c\vhdl\synth\synth.readme
mi2c\vhdl\synth
mi2c\vhdl\template\mi2c.bsf
mi2c\vhdl\template\mi2c.template
mi2c\vhdl\template\template.readme
mi2c\vhdl\template
mi2c\vhdl\vhdl.readme
mi2c\vhdl
mi2c