文件名称:verilog实现FSK
- 所属分类：
- VHDL编程
- 资源属性：
- [C/C++] [源码]
- 上传时间：
- 2009-05-04
- 文件大小：
- 3.82mb
- 下载次数：
- 0次
- 提 供 者：
- yfvictoria
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
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下载文件列表
压缩包 : DDSv4.0.rar 列表 DDSv4.0\DDSv4.0.prj DDSv4.0\DDSv4.0.prj.convert.8.1.bak DDSv4.0\designer\impl1\designer.log DDSv4.0\designer\impl1\designer_genhdl.log DDSv4.0\designer\impl1\Freq_Top.adb DDSv4.0\designer\impl1\Freq_Top.dtf\verify.log DDSv4.0\designer\impl1\Freq_Top.ide_des DDSv4.0\designer\impl1\Freq_Top.pdb DDSv4.0\designer\impl1\Freq_Top.pdb.depends DDSv4.0\designer\impl1\Freq_Top.tcl DDSv4.0\designer\impl1\Freq_Top_1.adb DDSv4.0\designer\impl1\Freq_Top_1.dtf\verify.log DDSv4.0\designer\impl1\Freq_Top_1.ide_des DDSv4.0\designer\impl1\Freq_Top_1.pdb DDSv4.0\designer\impl1\Freq_Top_1.pdb.depends DDSv4.0\designer\impl1\Freq_Top_1_fp\$$FlashPro_FPBBALTLPT1.L$$ DDSv4.0\designer\impl1\Freq_Top_1_fp\Freq_Top_1.log DDSv4.0\designer\impl1\Freq_Top_1_fp\Freq_Top_1.pro DDSv4.0\designer\impl1\Freq_Top_1_fp\projectData\Freq_Top_1.pdb DDSv4.0\designer\impl1\Freq_Top_fp\$$FlashPro_FPBBALTLPT1.L$$ DDSv4.0\designer\impl1\Freq_Top_fp\Freq_Top.log DDSv4.0\designer\impl1\Freq_Top_fp\Freq_Top.pro DDSv4.0\designer\impl1\Freq_Top_fp\projectData\Freq_Top.pdb DDSv4.0\hdl\actram.v DDSv4.0\hdl\basefreq.v DDSv4.0\hdl\bfctrl.v DDSv4.0\hdl\Clock_Gen.v DDSv4.0\hdl\ddf.v DDSv4.0\hdl\dds.v DDSv4.0\hdl\ddsCordic.v DDSv4.0\hdl\ddsHeader.h DDSv4.0\hdl\ffd.v DDSv4.0\hdl\kit.v DDSv4.0\hdl\LCD_Driver.v DDSv4.0\hdl\memWrap.v DDSv4.0\hdl\outfreq.v DDSv4.0\hdl\sel.v DDSv4.0\hdl\Sel_Ctrl.v DDSv4.0\simulation\modelsim.ini DDSv4.0\simulation\modelsim.ini.sav DDSv4.0\smartgen\pll_1m\pll_1m.cxf DDSv4.0\smartgen\pll_1m\pll_1m.gen DDSv4.0\smartgen\pll_1m\pll_1m.log DDSv4.0\smartgen\pll_1m\pll_1m.v DDSv4.0\smartgen\pll_1m_work.ixf DDSv4.0\smartgen\smartgen.aws DDSv4.0\synthesis\.recordref DDSv4.0\synthesis\backup\Freq_Top.srr DDSv4.0\synthesis\backup\Freq_Top_1.srr DDSv4.0\synthesis\Freq_Top.areasrr DDSv4.0\synthesis\Freq_Top.edn DDSv4.0\synthesis\Freq_Top.map DDSv4.0\synthesis\Freq_Top.sdf DDSv4.0\synthesis\Freq_Top.so DDSv4.0\synthesis\Freq_Top.srd DDSv4.0\synthesis\Freq_Top.srm DDSv4.0\synthesis\Freq_Top.srr DDSv4.0\synthesis\Freq_Top.srs DDSv4.0\synthesis\Freq_Top.tlg DDSv4.0\synthesis\Freq_Top_1.areasrr DDSv4.0\synthesis\Freq_Top_1.edn DDSv4.0\synthesis\Freq_Top_1.map DDSv4.0\synthesis\Freq_Top_1.sdf DDSv4.0\synthesis\Freq_Top_1.so DDSv4.0\synthesis\Freq_Top_1.srd DDSv4.0\synthesis\Freq_Top_1.srm DDSv4.0\synthesis\Freq_Top_1.srr DDSv4.0\synthesis\Freq_Top_1.srs DDSv4.0\synthesis\Freq_Top_1.tlg DDSv4.0\synthesis\Freq_Top_1_drc.rpt DDSv4.0\synthesis\Freq_Top_1_sdc.sdc DDSv4.0\synthesis\Freq_Top_drc.rpt DDSv4.0\synthesis\Freq_Top_sdc.sdc DDSv4.0\synthesis\Freq_Top_syn.prj DDSv4.0\synthesis\run_options.txt DDSv4.0\synthesis\stdout.log DDSv4.0\synthesis\syntmp\Freq_Top.msg DDSv4.0\synthesis\syntmp\Freq_Top.plg DDSv4.0\synthesis\syntmp\Freq_Top_1.msg DDSv4.0\synthesis\syntmp\Freq_Top_1.plg DDSv4.0\synthesis\traplog.tlg DDSv4.0\viewdraw\vf\project.lst DDSv4.0\viewdraw\viewdraw.ini DDSv4.0\designer\impl1\Freq_Top_1_fp\projectData DDSv4.0\designer\impl1\Freq_Top_fp\projectData DDSv4.0\designer\impl1\Freq_Top.dtf DDSv4.0\designer\impl1\Freq_Top_1.dtf DDSv4.0\designer\impl1\Freq_Top_1_fp DDSv4.0\designer\impl1\Freq_Top_fp DDSv4.0\designer\impl1\simulation DDSv4.0\designer\impl1 DDSv4.0\smartgen\pll_1m DDSv4.0\synthesis\backup DDSv4.0\synthesis\coreip DDSv4.0\synthesis\syntmp DDSv4.0\viewdraw\sch DDSv4.0\viewdraw\sym DDSv4.0\viewdraw\vf DDSv4.0\viewdraw\wir DDSv4.0\component DDSv4.0\constraint DDSv4.0\coreconsole DDSv4.0\designer DDSv4.0\hdl DDSv4.0\phy_synthesis DDSv4.0\simulation DDSv4.0\smartgen DDSv4.0\stimulus DDSv4.0\synthesis DDSv4.0\viewdraw DDSv4.0