文件名称:viterbi_node_sync_design
介绍说明－－下载内容均来自于网络，请自行研究使用
一个完整的viterbi译码程序和测试的程序
(系统自动生成,下载前可以参看下载内容)
下载文件列表
压缩包 : 55593403viterbi_node_sync_design.zip 列表 altera/ altera/design_examples/ altera/design_examples/viterbi_node_sync/ altera/design_examples/viterbi_node_sync/Quartus_II/ altera/design_examples/viterbi_node_sync/Quartus_II/run_script.tcl altera/design_examples/viterbi_node_sync/Quartus_II/viterbi_node_sync.qpf altera/design_examples/viterbi_node_sync/Quartus_II/viterbi_node_sync.qsf altera/design_examples/viterbi_node_sync/Quartus_II/wave.do altera/design_examples/viterbi_node_sync/source/ altera/design_examples/viterbi_node_sync/source/a_rcvsym.txt altera/design_examples/viterbi_node_sync/source/a_txsym.txt altera/design_examples/viterbi_node_sync/source/ber_node_sync.vhd altera/design_examples/viterbi_node_sync/source/BER_report.txt altera/design_examples/viterbi_node_sync/source/ber_threshold.vhd altera/design_examples/viterbi_node_sync/source/block_period_stim.txt altera/design_examples/viterbi_node_sync/source/mux_2d.vhd altera/design_examples/viterbi_node_sync/source/rotate_node_sync.vhd altera/design_examples/viterbi_node_sync/source/tcm_rcv_sector.txt altera/design_examples/viterbi_node_sync/source/transbit.txt altera/design_examples/viterbi_node_sync/source/viterbi_BER.bsf altera/design_examples/viterbi_node_sync/source/viterbi_BER.cmp altera/design_examples/viterbi_node_sync/source/viterbi_BER.html altera/design_examples/viterbi_node_sync/source/viterbi_BER.inc altera/design_examples/viterbi_node_sync/source/viterbi_BER.vhd altera/design_examples/viterbi_node_sync/source/viterbi_BER.vho altera/design_examples/viterbi_node_sync/source/viterbi_BER_bb.v altera/design_examples/viterbi_node_sync/source/viterbi_BER_inst.vhd altera/design_examples/viterbi_node_sync/source/viterbi_BER_logiclock_script.tcl altera/design_examples/viterbi_node_sync/source/viterbi_BER_testbench.vhd altera/design_examples/viterbi_node_sync/source/viterbi_BER_vital_script.tcl altera/design_examples/viterbi_node_sync/source/viterbi_BER_vsim_script.tcl altera/design_examples/viterbi_node_sync/source/viterbi_node_sync.vhd altera/design_examples/viterbi_node_sync/testbench/ altera/design_examples/viterbi_node_sync/testbench/auk_vit_vit_var_enc_arc_rtl.vhd altera/design_examples/viterbi_node_sync/testbench/auk_vit_vit_var_enc_ent.vhd altera/design_examples/viterbi_node_sync/testbench/Bench_vit_par_atl_arc_ben_node_sync.vhd altera/design_examples/viterbi_node_sync/testbench/Bench_vit_par_atl_ent_node_sync.vhd altera/design_examples/viterbi_node_sync/testbench/viterbi_node_sync_testbench.vhd altera/design_examples/viterbi_node_sync/testbench/vi_bench.vhd altera/design_examples/viterbi_node_sync/testbench/vi_functions.vhd altera/design_examples/viterbi_node_sync/testbench/vi_interface.vhd