文件名称:S1 CPU core
- 所属分类:
- VHDL编程
- 资源属性:
- [C/C++] [源码]
- 上传时间:
- 2022-05-01
- 文件大小:
- 1.06mb
- 下载次数:
- 0次
- 提 供 者:
- xptogudovan
- 相关连接:
- 无
- 下载说明:
- 别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容均来自于网络,请自行研究使用
S1 Core (codename Sirocco) is an open source hardware microprocessor design developed by Simply RISC. Based on Sun Microsystems' UltraSPARC T1, the S1 Core is licensed under the GNU General Public License, which is the license Sun chose for the OpenSPARC project.
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下载文件列表
压缩包 : s1_core.zip 列表 s1_core/ s1_core/docs/ s1_core/docs/INSTALL.txt s1_core/docs/LICENSE.txt s1_core/docs/other/ s1_core/docs/other/ACCESSES.txt s1_core/docs/other/BLOCKS.txt s1_core/docs/README.txt s1_core/docs/REQUIREMENTS.txt s1_core/docs/SIMULATION.txt s1_core/docs/SPEC.txt s1_core/docs/SUPPORT.txt s1_core/docs/SYNTHESIS.txt s1_core/docs/TODO.txt s1_core/docs/UPDATING.txt s1_core/hdl/ s1_core/hdl/behav/ s1_core/hdl/behav/sparc_libs/ s1_core/hdl/behav/sparc_libs/m1_lib.v s1_core/hdl/behav/sparc_libs/u1_lib.v s1_core/hdl/behav/testbench/ s1_core/hdl/behav/testbench/mem_harness.v s1_core/hdl/behav/testbench/s1_defs.h s1_core/hdl/behav/testbench/testbench.v s1_core/hdl/filelist.dc s1_core/hdl/filelist.fpga s1_core/hdl/filelist.icarus s1_core/hdl/filelist.vcs s1_core/hdl/filelist.xst s1_core/hdl/macrocell/ s1_core/hdl/macrocell/sparc_libs/ s1_core/hdl/rtl/ s1_core/hdl/rtl/s1_top/ s1_core/hdl/rtl/s1_top/int_ctrl.v s1_core/hdl/rtl/s1_top/rst_ctrl.v s1_core/hdl/rtl/s1_top/s1_defs.h s1_core/hdl/rtl/s1_top/s1_top.v s1_core/hdl/rtl/s1_top/spc2wbm.v s1_core/hdl/rtl/s1_top/t1_defs.h s1_core/hdl/rtl/sparc_core/ s1_core/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v s1_core/hdl/rtl/sparc_core/bw_r_dcd.v s1_core/hdl/rtl/sparc_core/bw_r_frf.v s1_core/hdl/rtl/sparc_core/bw_r_icd.v s1_core/hdl/rtl/sparc_core/bw_r_idct.v s1_core/hdl/rtl/sparc_core/bw_r_irf.v s1_core/hdl/rtl/sparc_core/bw_r_irf_register.v s1_core/hdl/rtl/sparc_core/bw_r_rf16x160.v s1_core/hdl/rtl/sparc_core/bw_r_rf16x32.v s1_core/hdl/rtl/sparc_core/bw_r_rf32x152b.v s1_core/hdl/rtl/sparc_core/bw_r_rf32x80.v s1_core/hdl/rtl/sparc_core/bw_r_scm.v s1_core/hdl/rtl/sparc_core/bw_r_tlb.v s1_core/hdl/rtl/sparc_core/cluster_header.v s1_core/hdl/rtl/sparc_core/cmp_sram_redhdr.v s1_core/hdl/rtl/sparc_core/cpx_spc_buf.v s1_core/hdl/rtl/sparc_core/cpx_spc_rpt.v s1_core/hdl/rtl/sparc_core/include/ s1_core/hdl/rtl/sparc_core/lsu.v s1_core/hdl/rtl/sparc_core/lsu_asi_decode.v s1_core/hdl/rtl/sparc_core/lsu_dcache_lfsr.v s1_core/hdl/rtl/sparc_core/lsu_dcdp.v s1_core/hdl/rtl/sparc_core/lsu_dctl.v s1_core/hdl/rtl/sparc_core/lsu_dctldp.v s1_core/hdl/rtl/sparc_core/lsu_dc_parity_gen.v s1_core/hdl/rtl/sparc_core/lsu_excpctl.v s1_core/hdl/rtl/sparc_core/lsu_pcx_qmon.v s1_core/hdl/rtl/sparc_core/lsu_qctl1.v s1_core/hdl/rtl/sparc_core/lsu_qctl2.v s1_core/hdl/rtl/sparc_core/lsu_qdp1.v s1_core/hdl/rtl/sparc_core/lsu_qdp2.v s1_core/hdl/rtl/sparc_core/lsu_rrobin_picker2.v s1_core/hdl/rtl/sparc_core/lsu_stb_ctl.v s1_core/hdl/rtl/sparc_core/lsu_stb_ctldp.v s1_core/hdl/rtl/sparc_core/lsu_stb_rwctl.v s1_core/hdl/rtl/sparc_core/lsu_stb_rwdp.v s1_core/hdl/rtl/sparc_core/lsu_tagdp.v s1_core/hdl/rtl/sparc_core/lsu_tlbdp.v s1_core/hdl/rtl/sparc_core/mul64.v s1_core/hdl/rtl/sparc_core/sparc.v s1_core/hdl/rtl/sparc_core/sparc_exu.v s1_core/hdl/rtl/sparc_core/sparc_exu_alu.v s1_core/hdl/rtl/sparc_core/sparc_exu_aluadder64.v s1_core/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v s1_core/hdl/rtl/sparc_core/sparc_exu_alulogic.v s1_core/hdl/rtl/sparc_core/sparc_exu_aluor32.v s1_core/hdl/rtl/sparc_core/sparc_exu_aluspr.v s1_core/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v s1_core/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v s1_core/hdl/rtl/sparc_core/sparc_exu_byp.v s1_core/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v s1_core/hdl/rtl/sparc_core/sparc_exu_div.v s1_core/hdl/rtl/sparc_core/sparc_exu_div_32eql.v s1_core/hdl/rtl/sparc_core/sparc_exu_div_yreg.v s1_core/hdl/rtl/sparc_core/sparc_exu_ecc.v s1_core/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v s1_core/hdl/rtl/sparc_core/sparc_exu_ecl.v s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v s1_core/hdl/rtl/sparc_core/sparc_exu_eclccr.v s1_core/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v s1_core/hdl/rtl/sparc_core/sparc_exu_reg.v s1_core/hdl/rtl/sparc_core/sparc_exu_rml.v s1_core/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v s1_core/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v s1_core/hdl/rtl/sparc_core/sparc_exu_rndrob.v s1_core/hdl/rtl/sparc_core/sparc_exu_shft.v s1_core/hdl/rtl/sparc_core/sparc_ffu.v s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl.v s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v s1_core/hdl/rtl/sparc_core/sparc_ffu_dp.v s1_core/hdl/rtl/sparc_core/sparc_ffu_part_add32.v s1_core/hdl/rtl/sparc_core/sparc_ffu_vis.v s1_core/hdl/rtl/sparc_core/sparc_ifu.v s1_core/hdl/rtl/sparc_core/sparc_ifu_cmp35.v s1_core/hdl/rtl/sparc_core/sparc_ifu_ctr5.v s1_core/hdl/rtl/sparc_core/sparc_ifu_dcl.v s1_core/hdl/rtl/sparc_core/sparc_ifu_dec.v s1_core/hdl/rtl/sparc_core/sparc_ifu_errctl.v s1_core/hdl/rtl/sparc_core/sparc_ifu_errdp.v s1_core/hdl/rtl/sparc_core/sparc_ifu_fcl.v s1_core/hdl/rtl/sparc_core/sparc_ifu_fdp.v s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v s1_core/hdl/rtl/sparc_core/sparc_ifu_imd.v s1_core/hdl/rtl/sparc_core/sparc_ifu_incr46.v s1_core/hdl/rtl/sparc_core/sparc_ifu_invctl.v s1_core/hdl