Parallel FIR filter is the prime block of many modern communication application such as MIMO, multi-point transceivers
etc. But hardware replication problem of parallel techniques make the system more bulky and costly. Fast FIR algorithm
(FFA) gives the best alternative to traditional parallel techniques. In this paper, FFA based FIR structures with different
topologies of multiplier and adder are implemented. To optimize design different multiplication technique like add and
shift method, Vedic multiplier and booth multiplier are used for computation. Various adders such as carry select adder,
carry save adder and Han-Carlson adder are analyzed for improved performance of the FFA structure. The basic objective
is to investigate the performance of these designs for the tradeoffs between area, delay and power dissipation. Comparative
study is carried out among conventional and different proposed designs. The advantage of presented work is that; based on
the constraints, one can select the suitable design for specific application. It also fulfils the literature gap of critical analysis
of FPGA implementation of FFA architecture using different multiplier and adder topologies. Xilinx Vivado HLS tool is
used to implement the proposed designs in VHDL.