压缩包 : 115157723m1_xsi_hdl.rar.zip 列表
5k_preset/
5k_preset/VHDL/
5k_preset/VHDL/preset_5k.log
5k_preset/VHDL/WORK/
5k_preset/VHDL/WORK/PRESET_5K.sim
5k_preset/VHDL/WORK/PRESET_5K__BEHAV.sim
5k_preset/VHDL/WORK/PRESET_5K.mra
5k_preset/VHDL/WORK/PRESET_5K.syn
5k_preset/VHDL/WORK/PRESET_5K__BEHAV.syn
5k_preset/VHDL/.synopsys_dc.setup
5k_preset/VHDL/command.log
5k_preset/VHDL/M1_files/
5k_preset/VHDL/M1_files/preset_5k.sxnf
5k_preset/VHDL/M1_files/preset_5k.ncf
5k_preset/VHDL/M1_files/command.his
5k_preset/VHDL/M1_files/ngdbuild.log
5k_preset/VHDL/M1_files/netlist.lst
5k_preset/VHDL/M1_files/preset_5k.ngo
5k_preset/VHDL/M1_files/preset_5k.ngd
5k_preset/VHDL/M1_files/preset_5k.bld
5k_preset/VHDL/M1_files/map.mrp
5k_preset/VHDL/M1_files/map.ngm
5k_preset/VHDL/M1_files/preset_5k.pcf
5k_preset/VHDL/M1_files/map.ncd
5k_preset/VHDL/M1_files/map.pcf
5k_preset/VHDL/M1_files/preset_5k.par
5k_preset/VHDL/M1_files/preset_5k.ncd
5k_preset/VHDL/M1_files/preset_5k.dly
5k_preset/VHDL/M1_files/preset_5k.pad
5k_preset/VHDL/M1_files/preset_5k.twr
5k_preset/VHDL/M1_files/time_sim.alf
5k_preset/VHDL/M1_files/time_sim.nga
5k_preset/VHDL/M1_files/time_sim.vhd
5k_preset/VHDL/M1_files/time_sim.sdf
5k_preset/VHDL/M1_files/preset_5k.bgn
5k_preset/VHDL/M1_files/preset_5k.drc
5k_preset/VHDL/M1_files/preset_5k.bit
5k_preset/VHDL/preset_5k.vhd
5k_preset/VHDL/preset_5k.script
5k_preset/VHDL/preset_5k.fpga
5k_preset/VHDL/preset_5k.timing
5k_preset/VHDL/preset_5k.sxnf
5k_preset/VHDL/preset_5k.db
5k_preset/VHDL/preset_5k.ncf
5k_preset/VHDL/dc2ncf.log
5k_preset/VHDL/preset_5k.dc
5k_preset/Verilog/
5k_preset/Verilog/preset_5k.v
5k_preset/Verilog/preset_5k.log
5k_preset/Verilog/.synopsys_dc.setup
5k_preset/Verilog/M1_files/
5k_preset/Verilog/M1_files/preset_5k.sxnf
5k_preset/Verilog/M1_files/preset_5k.ncf
5k_preset/Verilog/M1_files/command.his
5k_preset/Verilog/M1_files/ngdbuild.log
5k_preset/Verilog/M1_files/netlist.lst
5k_preset/Verilog/M1_files/preset_5k.ngo
5k_preset/Verilog/M1_files/preset_5k.ngd
5k_preset/Verilog/M1_files/preset_5k.bld
5k_preset/Verilog/M1_files/map.mrp
5k_preset/Verilog/M1_files/map.ngm
5k_preset/Verilog/M1_files/preset_5k.pcf
5k_preset/Verilog/M1_files/map.ncd
5k_preset/Verilog/M1_files/map.pcf
5k_preset/Verilog/M1_files/preset_5k.par
5k_preset/Verilog/M1_files/preset_5k.ncd
5k_preset/Verilog/M1_files/preset_5k.dly
5k_preset/Verilog/M1_files/preset_5k.pad
5k_preset/Verilog/M1_files/preset_5k.twr
5k_preset/Verilog/M1_files/time_sim.alf
5k_preset/Verilog/M1_files/time_sim.nga
5k_preset/Verilog/M1_files/time_sim.v
5k_preset/Verilog/M1_files/time_sim.sdf
5k_preset/Verilog/M1_files/time_sim.tv
5k_preset/Verilog/M1_files/time_sim.pin
5k_preset/Verilog/M1_files/preset_5k.bgn
5k_preset/Verilog/M1_files/preset_5k.drc
5k_preset/Verilog/M1_files/preset_5k.bit
5k_preset/Verilog/preset_5k.script
5k_preset/Verilog/command.log
5k_preset/Verilog/preset_5k.fpga
5k_preset/Verilog/preset_5k.timing
5k_preset/Verilog/preset_5k.sxnf
5k_preset/Verilog/preset_5k.db
5k_preset/Verilog/preset_5k.ncf
5k_preset/Verilog/dc2ncf.log
5k_preset/Verilog/preset_5k.dc
Barrel_SR/
Barrel_SR/VHDL/
Barrel_SR/VHDL/Barrel_Org/
Barrel_SR/VHDL/Barrel_Org/WORK/
Barrel_SR/VHDL/Barrel_Org/WORK/BARREL_ORG.sim
Barrel_SR/VHDL/Barrel_Org/WORK/BARREL_ORG__RTL.sim
Barrel_SR/VHDL/Barrel_Org/WORK/BARREL_ORG.mra
Barrel_SR/VHDL/Barrel_Org/WORK/BARREL_ORG.syn
Barrel_SR/VHDL/Barrel_Org/WORK/BARREL_ORG__RTL.syn
Barrel_SR/VHDL/Barrel_Org/barrel_org.script
Barrel_SR/VHDL/Barrel_Org/barrel_org.vhd
Barrel_SR/VHDL/Barrel_Org/command.log
Barrel_SR/VHDL/Barrel_Org/.synopsys_dc.setup
Barrel_SR/VHDL/Barrel_Org/M1_files/
Barrel_SR/VHDL/Barrel_Org/M1_files/barrel_org.sxnf
Barrel_SR/VHDL/Barrel_Org/M1_files/barrel_org.ncf
Barrel_SR/VHDL/Barrel_Org/M1_files/command.his
Barrel_SR/VHDL/Barrel_Org/M1_files/ngdbuild.log
Barrel_SR/VHDL/Barrel_Org/M1_files/netlist.lst
Barrel_SR/VHDL/Barrel_Org/M1_files/barrel_org.ngo
Barrel_SR/VHDL/Barrel_Org/M1_files/barrel_org.ngd
Barrel_SR/VHDL/Barrel_Org/M1_files/barrel_org.bld
Barrel_SR/VHDL/Barrel_Org/M1_files/map.mrp
Barrel_SR/VHDL/Barrel_Org/M1_files/map.ngm
Barrel_SR/VHDL/Barrel_Org/M1_files/barrel_org.pcf
Barrel_SR/VHDL/Barrel_Org/M1_files/map.ncd
Barrel_SR/VHDL/Barrel_Org/M1_files/map.pcf
Barrel_SR/VHDL/Barrel_Org/M1_files/barrel_org.par
Barrel_SR/VHDL/Barrel_Org/M1_files/barrel_org.ncd
Barrel_SR/VHDL/Barrel_Org/M1_files/barrel_org.dly
Barrel_SR/VHDL/Barrel_Org/M1_files/barrel_org.pad
Barrel_SR/VHDL/Barrel_Org/M1_files/barrel_org.twr
Barrel_SR/VHDL/Barrel_Org/M1_files/time_sim.alf
Barrel_SR/VHDL/Barrel_Org/M1_files/time_sim.nga
Barrel_SR/VHDL/Barrel_Org/M1_files/time_sim.vhd
Barrel_SR/VHDL/Barrel_Org/M1_files/time_sim.sdf
Barrel_SR/VHDL/Barrel_Org/M1_files/barrel_org.bgn
Barrel_SR/VHDL/Barrel_Org/M1_files/barrel_org.drc
Barrel_SR/VHDL/Barrel_Org/M1_files/barrel_org.bit
Barrel_SR/VHDL/Barrel_Org/barrel_org.log
Barrel_SR/VHDL/Barrel_Org/barrel_org.fpga
Barrel_SR/VHDL/Barrel_Org/barrel_org.timing
Barrel_SR/VHDL/Barrel_Org/barrel_org.sxnf
Barrel_SR/VHDL/Barrel_Org/barrel_org.db
Barrel_SR/VHDL/Barrel_Org/barrel_org.ncf
Barrel_SR/VHDL/Barrel_Org/dc2ncf.log
Barrel_SR/VHDL/Barrel_Org/barrel_org.dc
Barrel_SR/VHDL/.synopsys_dc.setup
Barrel_SR/VHDL/Barrel/
Barrel_SR/VHDL/Barrel/barrel.vhd
Barrel_SR/VHDL/Barrel/WORK/
Barrel_SR/VHDL/Barrel/WORK/BARREL.sim
Barrel_SR/VHDL/Barrel/WORK/BARREL__RTL.sim
Barrel_SR/VHDL/Barrel/WORK/BARREL.mra
Barrel_SR/VHDL/Barrel/WORK/BARREL.syn
Barrel_SR/VHDL/Barrel/WORK/BARREL__RTL.syn
Barrel_SR/VHDL/Barrel/barrel.script
Barrel_SR/VHDL/Barrel/barrel.log
Barrel_SR/VHDL/Barrel/M1_files/
Barrel_SR/VHDL/Barrel/M1_files/barrel.sxnf
Barrel_SR/VHDL/Barrel/M1_files/barrel.ncf
Barrel_SR/VHDL/Barrel/M1_files/command.his
Barrel_SR/VHDL/Barrel/M1_files/ngdbuild.log
Barrel_SR/VHDL/Barrel/M1_files/netlist.lst
Barrel_SR/VHDL/Barrel/M1_files/barrel.ngo
Barrel_SR/VHDL/Barrel/M1_files/barrel.ngd
Barrel_SR/VHDL/Barrel/M1_files/barrel.bld
Barrel_SR/VHDL/Barrel/M1_files/map.mrp
Barrel_SR/VHDL/Barrel/M1_files/map.ngm
Barrel_SR/VHDL/Barrel/M1_files/barrel.pcf
Barrel_SR/VHDL/Barrel/M1_files/map.ncd
Barrel_SR/VHDL/Barrel/M1_files/map.pcf
Barrel_SR/VHDL/Barrel/M1_files/barrel.par
Barrel_SR/VHDL/Barrel/M1_files/barrel.ncd
Barrel_SR/VHDL/Barrel/M1_files/barrel.dly
Barrel_SR/VHDL/Barrel/M1_files/barrel.pad
Barrel_SR/VHDL/Barrel/M1_files/barrel.twr
Barrel_SR/VHDL/Barrel/M1_files/time_sim.alf
Barrel_SR/VHDL/Barrel/M1_files/time_sim.nga
Barrel_SR/VHDL/Barrel/M1_files/time_sim.vhd
Barrel_SR/VHDL/Barrel/M1_files/time_sim.sdf
Barrel_SR/VHDL/Barrel/M1_files/barrel.bgn
Barrel_SR/VHDL/Barrel/M1_files/barrel.drc
Barrel_SR/VHDL/Barrel/M1_files/barrel.bit
Barrel_SR/VHDL/Barrel/command.log
Barrel_SR/VHDL/Barrel/barrel.fpga
Barrel_SR/VHDL/Barrel/barrel.timing
Barrel_SR/VHDL/Barrel/barrel.sxnf
Barrel_SR/VHDL/Barrel/barrel.db
Barrel_SR/VHDL/Barrel/barrel.ncf
Barrel_SR/VHDL/Barrel/.synopsys_dc.setup
Barrel_SR/VHDL/Barrel/dc2ncf.log
Barrel_SR/VHDL/Barrel/barrel.dc
Barrel_SR/Verilog/
Barrel_SR/Verilog/Barrel_org/
Barrel_SR/Verilog/Barrel_org/command.log
Barrel_SR/Verilog/Barrel_org/barrel_org.v
Barrel_SR/Verilog/Barrel_org/.synopsys_dc.setup
Barrel_SR/Verilog/Barrel_org/barrel_org.script
Barrel_SR/Verilog/Barrel_org/barrel_org.log
Barrel_SR/Verilog/Barrel_org/M1_files/
Barrel_SR/Verilog/Barrel_org/M1_files/barrel_org.sxnf
Barrel_SR/Verilog/Barrel_org/M1_files/barrel_org.ncf
Barrel_SR/Verilog/Barrel_org/M1_files/command.his
Barrel_SR/Verilog/Barrel_org/M1_files/ngdbuild.log
Barrel_SR/Verilog/Barrel_org/M1_files/netlist.lst
Barrel_SR/Verilog/Barrel_org/M1_files/barrel_org.ngo
Barrel_SR/Verilog/Barrel_org/M1_files/barrel_org.ngd
Barrel_SR/Verilog/Barrel_org/M1_files/barrel_org.bld
Barrel_SR/Verilog/Barrel_org/M1_files/map.mrp
Barrel_SR/Verilog/Barrel_org/M1_files/map.ngm
Barrel_SR/Verilog/Barrel_org/M1_files/barrel_org.pcf
Barrel_SR/Verilog/Barrel_org/M1_files/map.ncd
Barrel_SR/Verilog/Barrel_org/M1_files/map.pcf
Barrel_SR/Verilog/Barrel_org/M1_files/barrel_org.par
Barrel_SR/Verilog/Barrel_org/M1_files/barrel_org.ncd
Barrel_SR/Verilog/Barrel_org/M1_files/barrel_org.dly
Barrel_SR/Verilog/Barrel_org/M1_files/barrel_org.pad
Barrel_SR/Verilog/Barrel_org/M1_files/barrel_org.twr
Barrel_SR/Verilog/Barrel_org/M1_files/time_sim.alf
Barrel_SR/Verilog/Barrel_org/M1_files/time_sim.nga
Barrel_SR/Verilog/Barrel_org/M1_files/time_sim.v
Barrel_SR/Verilog/Barrel_org/M1_files/time_sim.sdf
Barrel_SR/Verilog/Barrel_org/M1_files/time_sim.tv
Barrel_SR/Verilog/Barrel_org/M1_files/time_sim.pin
Barrel_SR/Verilog/Barrel_org/M1_files/barrel_org.bgn
Barrel_SR/Verilog/Barrel_org/M1_files/barrel_org.drc
Barrel_SR/Verilog/Barrel_org/M1_files/barrel_org.bit
Barrel_SR/Verilog/Barrel_org/barrel_org.fpga
Barrel_SR/Verilog/Barrel_org/barrel_org.timing
Barrel_SR/Verilog/Barrel_org/barrel_org.sxnf
Barrel_SR/Verilog/Barrel_org/barrel_org.db
Barrel_SR/Verilog/Barrel_org/barrel_org.ncf
Barrel_SR/Verilog/Barrel_org/dc2ncf.log
Barrel_SR/Verilog/Barrel_org/barrel_org.dc
Barrel_SR/Verilog/.synopsys_dc.setup
Barrel_SR/Verilog/Barrel/
Barrel_SR/Verilog/Barrel/M1_files/
Barrel_SR/Verilog/Barrel/M1_files/barrel.sxnf
Barrel_SR/Verilog/Barrel/M1_files/barrel.ncf
Barrel_SR/Verilog/Barrel/M1_files/command.his
Barrel_SR/Verilog/Barrel/M1_files/ngdbuild.log
Barrel_SR/Verilog/Barrel/M1_files/netlist.lst
Barrel_SR/Verilog/Barrel/M1_files/barrel.ngo
Barrel_SR/Verilog/Barrel/M1_files/barrel.ngd
Barrel_SR/Verilog/Barrel/M1_files/barrel.bld
Barrel_SR/Verilog/Barrel/M1_files/map.mrp
Barrel_SR/Verilog/Barrel/M1_files/map.ngm
Barrel_SR/Verilog/Barrel/M1_files/barrel.pcf
Barrel_SR/Verilog/Barrel/M1_files/map.ncd
Barrel_SR/Verilog/Barrel/M1_files/map.pcf
Barrel_SR/Verilog/Barrel/M1_files/barrel.par
Barrel_SR/Verilog/Barrel/M1_files/barrel.ncd
Barrel_SR/Verilog/Barrel/M1_files/barrel.dly
Barrel_SR/Verilog/Barrel/M1_files/barrel.pad
Barrel_SR/Verilog/Barrel/M1_files/barrel.twr
Barrel_SR/Verilog/Barrel/M1_files/time_sim.alf
Barrel_SR/Verilog/Barrel/M1_files/time_sim.nga
Barrel_SR/Verilog/Barrel/M1_files/time_sim.v
Barrel_SR/Verilog/Barrel/M1_files/time_sim.sdf
Barrel_SR/Verilog/Barrel/M1_files/time_sim.tv
Barrel_SR/Verilog/Barrel/M1_files/time_sim.pin
Barrel_SR/Verilog/Barrel/M1_files/barrel.bgn
Barrel_SR/Verilog/Barrel/M1_files/barrel.drc
Barrel_SR/Verilog/Barrel/M1_files/barrel.bit
Barrel_SR/Verilog/Barrel/barrel.log
Barrel_SR/Verilog/Barrel/command.log
Barrel_SR/Verilog/Barrel/barrel.script
Barrel_SR/Verilog/Barrel/barrel.fpga
Barrel_SR/Verilog/Barrel/barrel.timing
Barrel_SR/Verilog/Barrel/barrel.v
Barrel_SR/Verilog/Barrel/barrel.sxnf
Barrel_SR/Verilog/Barrel/barrel.db
Barrel_SR/Verilog/Barrel/.synopsys_dc.setup
Barrel_SR/Verilog/Barrel/barrel.dc
Barrel_SR/Verilog/Barrel/dc2ncf.log
Barrel_SR/Verilog/Barrel/barrel.ncf
Bidir_LogiBLOX/
Bidir_LogiBLOX/VHDL/
Bidir_LogiBLOX/VHDL/logiblox.log
Bidir_LogiBLOX/VHDL/bidir_logiblox.vhd
Bidir_LogiBLOX/VHDL/.synopsys_dc.setup
Bidir_LogiBLOX/VHDL/bidir_logiblox.script
Bidir_LogiBLOX/VHDL/bidir_io_from_lb.vhd
Bidir_LogiBLOX/VHDL/bidir_io_from_lb.vhi
Bidir_LogiBLOX/VHDL/bidir_io_from_lb.ngo
Bidir_LogiBLOX/VHDL/bidir_io_from_lb.mod
Bidir_LogiBLOX/VHDL/logiblox.ini
Bidir_LogiBLOX/VHDL/bidir_logiblox.log
Bidir_LogiBLOX/VHDL/WORK/
Bidir_LogiBLOX/VHDL/WORK/BIDIR_LOGIBLOX.sim
Bidir_LogiBLOX/VHDL/WORK/BIDIR_LOGIBLOX__XILINX.sim
Bidir_LogiBLOX/VHDL/WORK/BIDIR_LOGIBLOX.mra
Bidir_LogiBLOX/VHDL/WORK/BIDIR_LOGIBLOX.syn
Bidir_LogiBLOX/VHDL/WORK/BIDIR_LOGIBLOX__XILINX.syn
Bidir_LogiBLOX/VHDL/M1_files/
Bidir_LogiBLOX/VHDL/M1_files/bidir_logiblox.sxnf
Bidir_LogiBLOX/VHDL/M1_files/bidir_logiblox.ncf
Bidir_LogiBLOX/VHDL/M1_files/bidir_io_from_lb.ngo
Bidir_LogiBLOX/VHDL/M1_files/command.his
Bidir_LogiBLOX/VHDL/M1_files/ngdbuild.log
Bidir_LogiBLOX/VHDL/M1_files/netlist.lst
Bidir_LogiBLOX/VHDL/M1_files/bidir_logiblox.ngo
Bidir_LogiBLOX/VHDL/M1_files/bidir_logiblox.ngd
Bidir_LogiBLOX/VHDL/M1_files/bidir_logiblox.bld
Bidir_LogiBLOX/VHDL/M1_files/map.mrp
Bidir_LogiBLOX/VHDL/M1_files/map.ngm
Bidir_LogiBLOX/VHDL/M1_files/bidir_logiblox.pcf
Bidir_LogiBLOX/VHDL/M1_files/map.ncd
Bidir_LogiBLOX/VHDL/M1_files/map.pcf
Bidir_LogiBLOX/VHDL/M1_files/bidir_logiblox.par
Bidir_LogiBLOX/VHDL/M1_files/bidir_logiblox.ncd
Bidir_LogiBLOX/VHDL/M1_files/bidir_logiblox.dly
Bidir_LogiBLOX/VHDL/M1_files/bidir_logiblox.pad
Bidir_LogiBLOX/VHDL/M1_files/bidir_logiblox.twr
Bidir_LogiBLOX/VHDL/M1_files/time_sim.alf
Bidir_LogiBLOX/VHDL/M1_files/time_sim.nga
Bidir_LogiBLOX/VHDL/M1_files/time_sim.vhd
Bidir_LogiBLOX/VHDL/M1_files/time_sim.sdf
Bidir_LogiBLOX/VHDL/M1_files/bidir_logiblox.bgn
Bidir_LogiBLOX/VHDL/M1_files/bidir_logiblox.drc
Bidir_LogiBLOX/VHDL/M1_files/bidir_logiblox.bit
Bidir_LogiBLOX/VHDL/command.log
Bidir_LogiBLOX/VHDL/bidir_logiblox.fpga
Bidir_LogiBLOX/VHDL/bidir_logiblox.timing
Bidir_LogiBLOX/VHDL/dc2ncf.log
Bidir_LogiBLOX/VHDL/bidir_logiblox.db
Bidir_LogiBLOX/VHDL/bidir_logiblox.sxnf
Bidir_LogiBLOX/VHDL/bidir_logiblox.ncf
Bidir_LogiBLOX/VHDL/view_command.log
Bidir_LogiBLOX/VHDL/bidir_logiblox.dc
Bidir_LogiBLOX/Verilog/
Bidir_LogiBLOX/Verilog/logiblox.log
Bidir_LogiBLOX/Verilog/bidir_logiblox.v
Bidir_LogiBLOX/Verilog/.synopsys_dc.setup
Bidir_LogiBLOX/Verilog/bidir_logiblox.script
Bidir_LogiBLOX/Verilog/bidir_io_from_lb.ngo
Bidir_LogiBLOX/Verilog/bidir_io_from_lb.v
Bidir_LogiBLOX/Verilog/bidir_io_from_lb.vei
Bidir_LogiBLOX/Verilog/bidir_io_from_lb.mod
Bidir_LogiBLOX/Verilog/logiblox.ini
Bidir_LogiBLOX/Verilog/bidir_logiblox.log
Bidir_LogiBLOX/Verilog/M1_files/
Bidir_LogiBLOX/Verilog/M1_files/bidir_logiblox.sxnf
Bidir_LogiBLOX/Verilog/M1_files/bidir_logiblox.ncf
Bidir_LogiBLOX/Verilog/M1_files/bidir_io_from_lb.ngo
Bidir_LogiBLOX/Verilog/M1_files/command.his
Bidir_LogiBLOX/Verilog/M1_files/ngdbuild.log
Bidir_LogiBLOX/Verilog/M1_files/netlist.lst
Bidir_LogiBLOX/Verilog/M1_files/bidir_logiblox.ngo
Bidir_LogiBLOX/Verilog/M1_files/bidir_logiblox.ngd
Bidir_LogiBLOX/Verilog/M1_files/bidir_logiblox.bld
Bidir_LogiBLOX/Verilog/M1_files/map.mrp
Bidir_LogiBLOX/Verilog/M1_files/map.ngm
Bidir_LogiBLOX/Verilog/M1_files/bidir_logiblox.pcf
Bidir_LogiBLOX/Verilog/M1_files/map.ncd
Bidir_LogiBLOX/Verilog/M1_files/map.pcf
Bidir_LogiBLOX/Verilog/M1_files/bidir_logiblox.par
Bidir_LogiBLOX/Verilog/M1_files/bidir_logiblox.ncd
Bidir_LogiBLOX/Verilog/M1_files/bidir_logiblox.dly
Bidir_LogiBLOX/Verilog/M1_files/bidir_logiblox.pad
Bidir_LogiBLOX/Verilog/M1_files/bidir_logiblox.twr
Bidir_LogiBLOX/Verilog/M1_files/time_sim.v
Bidir_LogiBLOX/Verilog/M1_files/time_sim.alf
Bidir_LogiBLOX/Verilog/M1_files/time_sim.nga
Bidir_LogiBLOX/Verilog/M1_files/time_sim.sdf
Bidir_LogiBLOX/Verilog/M1_files/time_sim.tv
Bidir_LogiBLOX/Verilog/M1_files/time_sim.pin
Bidir_LogiBLOX/Verilog/M1_files/bidir_logiblox.bgn
Bidir_LogiBLOX/Verilog/M1_files/bidir_logiblox.drc
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GR_5K/VHDL/No_GR/M1_files/command.his
GR_5K/VHDL/No_GR/M1_files/ngdbuild.log
GR_5K/VHDL/No_GR/M1_files/netlist.lst
GR_5K/VHDL/No_GR/M1_files/no_gr.ngo
GR_5K/VHDL/No_GR/M1_files/no_gr.ngd
GR_5K/VHDL/No_GR/M1_files/no_gr.bld
GR_5K/VHDL/No_GR/M1_files/map.mrp
GR_5K/VHDL/No_GR/M1_files/map.ngm
GR_5K/VHDL/No_GR/M1_files/no_gr.pcf
GR_5K/VHDL/No_GR/M1_files/map.ncd
GR_5K/VHDL/No_GR/M1_files/map.pcf
GR_5K/VHDL/No_GR/M1_files/no_gr.par
GR_5K/VHDL/No_GR/M1_files/no_gr.ncd
GR_5K/VHDL/No_GR/M1_files/no_gr.dly
GR_5K/VHDL/No_GR/M1_files/no_gr.pad
GR_5K/VHDL/No_GR/M1_files/no_gr.twr
GR_5K/VHDL/No_GR/M1_files/time_sim.alf
GR_5K/VHDL/No_GR/M1_files/time_sim.nga
GR_5K/VHDL/No_GR/M1_files/time_sim.vhd
GR_5K/VHDL/No_GR/M1_files/time_sim.sdf
GR_5K/VHDL/No_GR/M1_files/no_gr.bgn
GR_5K/VHDL/No_GR/M1_files/no_gr.drc
GR_5K/VHDL/No_GR/M1_files/no_gr.bit
GR_5K/VHDL/No_GR/no_gr.script
GR_5K/VHDL/No_GR/no_gr.sxnf
GR_5K/VHDL/No_GR/command.log
GR_5K/VHDL/No_GR/no_gr.fpga
GR_5K/VHDL/No_GR/no_gr.timing
GR_5K/VHDL/No_GR/no_gr.ncf
GR_5K/VHDL/No_GR/dc2ncf.log
GR_5K/VHDL/No_GR/no_gr.dc
GR_5K/VHDL/No_GR/no_gr.db
GR_5K/VHDL/Active_low_GR/
GR_5K/VHDL/Active_low_GR/active_low_gr.vhd
GR_5K/VHDL/Active_low_GR/WORK/
GR_5K/VHDL/Active_low_GR/WORK/ACTIVE_LOW_GR.sim
GR_5K/VHDL/Active_low_GR/WORK/ACTIVE_LOW_GR__XILINX.sim
GR_5K/VHDL/Active_low_GR/WORK/ACTIVE_LOW_GR.mra
GR_5K/VHDL/Active_low_GR/WORK/ACTIVE_LOW_GR.syn
GR_5K/VHDL/Active_low_GR/WORK/ACTIVE_LOW_GR__XILINX.syn
GR_5K/VHDL/Active_low_GR/.synopsys_dc.setup
GR_5K/VHDL/Active_low_GR/command.log
GR_5K/VHDL/Active_low_GR/M1_files/
GR_5K/VHDL/Active_low_GR/M1_files/active_low_gr.sxnf
GR_5K/VHDL/Active_low_GR/M1_files/active_low_gr.ncf
GR_5K/VHDL/Active_low_GR/M1_files/command.his
GR_5K/VHDL/Active_low_GR/M1_files/ngdbuild.log
GR_5K/VHDL/Active_low_GR/M1_files/netlist.lst
GR_5K/VHDL/Active_low_GR/M1_files/active_low_gr.ngo
GR_5K/VHDL/Active_low_GR/M1_files/active_low_gr.ngd
GR_5K/VHDL/Active_low_GR/M1_files/active_low_gr.bld
GR_5K/VHDL/Active_low_GR/M1_files/map.mrp
GR_5K/VHDL/Active_low_GR/M1_files/map.ngm
GR_5K/VHDL/Active_low_GR/M1_files/active_low_gr.pcf
GR_5K/VHDL/Active_low_GR/M1_files/map.ncd
GR_5K/VHDL/Active_low_GR/M1_files/map.pcf
GR_5K/VHDL/Active_low_GR/M1_files/active_low_gr.par
GR_5K/VHDL/Active_low_GR/M1_files/active_low_gr.ncd
GR_5K/VHDL/Active_low_GR/M1_files/active_low_gr.dly
GR_5K/VHDL/Active_low_GR/M1_files/active_low_gr.pad
GR_5K/VHDL/Active_low_GR/M1_files/active_low_gr.twr
GR_5K/VHDL/Active_low_GR/M1_files/time_sim.alf
GR_5K/VHDL/Active_low_GR/M1_files/time_sim.nga
GR_5K/VHDL/Active_low_GR/M1_files/time_sim.vhd
GR_5K/VHDL/Active_low_GR/M1_files/time_sim.sdf
GR_5K/VHDL/Active_low_GR/M1_files/active_low_gr.bgn
GR_5K/VHDL/Active_low_GR/M1_files/active_low_gr.drc
GR_5K/VHDL/Active_low_GR/M1_files/active_low_gr.bit
GR_5K/VHDL/Active_low_GR/active_low_gr.log
GR_5K/VHDL/Active_low_GR/active_low_gr.script
GR_5K/VHDL/Active_low_GR/active_low_gr.fpga
GR_5K/VHDL/Active_low_GR/active_low_gr.timing
GR_5K/VHDL/Active_low_GR/dc2ncf.log
GR_5K/VHDL/Active_low_GR/active_low_gr.db
GR_5K/VHDL/Active_low_GR/active_low_gr.sxnf
GR_5K/VHDL/Active_low_GR/active_low_gr.ncf
GR_5K/VHDL/Active_low_GR/active_low_gr.dc
GR_5K/Verilog/
GR_5K/Verilog/Use_GR/
GR_5K/Verilog/Use_GR/use_gr.v
GR_5K/Verilog/Use_GR/use_gr.log
GR_5K/Verilog/Use_GR/.synopsys_dc.setup
GR_5K/Verilog/Use_GR/M1_files/
GR_5K/Verilog/Use_GR/M1_files/use_gr.sxnf
GR_5K/Verilog/Use_GR/M1_files/use_gr.ncf
GR_5K/Verilog/Use_GR/M1_files/command.his
GR_5K/Verilog/Use_GR/M1_files/ngdbuild.log
GR_5K/Verilog/Use_GR/M1_files/netlist.lst
GR_5K/Verilog/Use_GR/M1_files/use_gr.ngo
GR_5K/Verilog/Use_GR/M1_files/use_gr.ngd
GR_5K/Verilog/Use_GR/M1_files/use_gr.bld
GR_5K/Verilog/Use_GR/M1_files/map.mrp
GR_5K/Verilog/Use_GR/M1_files/map.ngm
GR_5K/Verilog/Use_GR/M1_files/use_gr.pcf
GR_5K/Verilog/Use_GR/M1_files/map.ncd
GR_5K/Verilog/Use_GR/M1_files/map.pcf
GR_5K/Verilog/Use_GR/M1_files/use_gr.par
GR_5K/Verilog/Use_GR/M1_files/use_gr.ncd
GR_5K/Verilog/Use_GR/M1_files/use_gr.dly
GR_5K/Verilog/Use_GR/M1_files/use_gr.pad
GR_5K/Verilog/Use_GR/M1_files/use_gr.twr
GR_5K/Verilog/Use_GR/M1_files/time_sim.alf
GR_5K/Verilog/Use_GR/M1_files/time_sim.nga
GR_5K/Verilog/Use_GR/M1_files/time_sim.v
GR_5K/Verilog/Use_GR/M1_files/time_sim.sdf
GR_5K/Verilog/Use_GR/M1_files/time_sim.tv
GR_5K/Verilog/Use_GR/M1_files/time_sim.pin
GR_5K/Verilog/Use_GR/M1_files/use_gr.bgn
GR_5K/Verilog/Use_GR/M1_files/use_gr.drc
GR_5K/Verilog/Use_GR/M1_files/use_gr.bit
GR_5K/Veri