压缩包 : 11912885syn_tutorial.zip 列表
eco_tutorial/
eco_tutorial/.synopsys_dc.setup
eco_tutorial/db/
eco_tutorial/db/eco_implemented.db
eco_tutorial/db/eco_optimized.db
eco_tutorial/db/eco_recycled.db
eco_tutorial/db/new_hdl.db
eco_tutorial/db/new_netlist.db
eco_tutorial/db/old_hdl.db
eco_tutorial/db/old_netlist.db
eco_tutorial/db/old_net_u.db
eco_tutorial/README
eco_tutorial/reports/
eco_tutorial/scripts/
eco_tutorial/scripts/create_db.scr
eco_tutorial/scripts/eco.script
eco_tutorial/scripts/spare_cell
eco_tutorial/scripts/uwave_ctl.pdef
eco_tutorial/src/
eco_tutorial/src/nu_uwave.v
eco_tutorial/src/nu_uwave.vhd
eco_tutorial/src/uwave.v
eco_tutorial/src/uwave.vhd
eco_tutorial/work/
examples/
examples/bc_view/
examples/bc_view/verilog/
examples/bc_view/verilog/.synopsys_dc.setup
examples/bc_view/verilog/db/
examples/bc_view/verilog/db/example.db
examples/bc_view/verilog/example.proj
examples/bc_view/verilog/hdl/
examples/bc_view/verilog/hdl/example.v
examples/bc_view/verilog/hdl/mult_proc.v
examples/bc_view/verilog/mult_proc.scr
examples/bc_view/verilog/rams/
examples/bc_view/verilog/rams/cs_rams.sl
examples/bc_view/verilog/rams/cs_rams.sldb
examples/bc_view/verilog/reports/
examples/bc_view/verilog/reports/example.rpt
examples/bc_view/verilog/scr/
examples/bc_view/verilog/scr/example.scr
examples/bc_view/verilog/soln/
examples/bc_view/verilog/soln/mult_proc.v
examples/bc_view/verilog/work/
examples/bc_view/verilog/work/example%verilog.syn
examples/bc_view/verilog/work/example%verilog__verilog.syn
examples/bc_view/verilog/work/EXAMPLE.mr
examples/bc_view/verilog/work/example.v.bi
examples/bc_view/verilog/work/example.v.id
examples/bc_view/vhdl/
examples/bc_view/vhdl/.synopsys_dc.setup
examples/bc_view/vhdl/db/
examples/bc_view/vhdl/db/example.db
examples/bc_view/vhdl/example.proj
examples/bc_view/vhdl/hdl/
examples/bc_view/vhdl/hdl/example.vhd
examples/bc_view/vhdl/hdl/mult_proc.vhd
examples/bc_view/vhdl/mult_proc.scr
examples/bc_view/vhdl/rams/
examples/bc_view/vhdl/rams/cs_rams.sl
examples/bc_view/vhdl/rams/cs_rams.sldb
examples/bc_view/vhdl/reports/
examples/bc_view/vhdl/reports/example.rpt
examples/bc_view/vhdl/scr/
examples/bc_view/vhdl/scr/example.scr
examples/bc_view/vhdl/soln/
examples/bc_view/vhdl/soln/mult_proc.vhd
examples/bc_view/vhdl/work/
examples/bc_view/vhdl/work/EXAMPLE.mr
examples/bc_view/vhdl/work/EXAMPLE.st
examples/bc_view/vhdl/work/EXAMPLE.syn
examples/bc_view/vhdl/work/example.vhd.bi
examples/bc_view/vhdl/work/example.vhd.id
examples/bc_view/vhdl/work/EXAMPLE__BEHAVIORAL.st
examples/bc_view/vhdl/work/EXAMPLE__BEHAVIORAL.syn
examples/dotfiles/
examples/dotfiles/cshrc
examples/dotfiles/nm_rules.dcsh
examples/dotfiles/synopsys
examples/dotfiles/Xdefaults
examples/fsm/
examples/fsm/.synopsys_dc.setup
examples/fsm/proc2.db
examples/fsm/proc2.v
examples/fsm/proc2.vhd
examples/fsm/proc3.db
examples/fsm/proc3.v
examples/fsm/proc3.vhd
examples/fsm/proc4.db
examples/fsm/proc4.v
examples/fsm/proc4.vhd
examples/fsm/work/
examples/README
examples/rtl_analyzer/
examples/rtl_analyzer/verilog/
examples/rtl_analyzer/verilog/.synopsys_dc.setup
examples/rtl_analyzer/verilog/clean
examples/rtl_analyzer/verilog/gtech/
examples/rtl_analyzer/verilog/gtech/addr_combo.ra
examples/rtl_analyzer/verilog/gtech/addr_combo.v.bi
examples/rtl_analyzer/verilog/gtech/addr_combo.v.id
examples/rtl_analyzer/verilog/gtech/addr_fsm.ra
examples/rtl_analyzer/verilog/gtech/addr_fsm.v.bi
examples/rtl_analyzer/verilog/gtech/addr_fsm.v.id
examples/rtl_analyzer/verilog/gtech/top.ra
examples/rtl_analyzer/verilog/gtech/top.v.bi
examples/rtl_analyzer/verilog/gtech/top.v.id
examples/rtl_analyzer/verilog/gtech_fast/
examples/rtl_analyzer/verilog/hdl/
examples/rtl_analyzer/verilog/hdl/addr_combo.v
examples/rtl_analyzer/verilog/hdl/addr_combo_fast.v
examples/rtl_analyzer/verilog/hdl/addr_fsm.v
examples/rtl_analyzer/verilog/hdl/top.v
examples/rtl_analyzer/verilog/libs/
examples/rtl_analyzer/verilog/libs/class.db
examples/rtl_analyzer/verilog/mapped/
examples/rtl_analyzer/verilog/mapped/top_mapped.db
examples/rtl_analyzer/verilog/projs/
examples/rtl_analyzer/verilog/projs/top_cons.scr
examples/rtl_analyzer/verilog/projs/top_gtech.proj
examples/rtl_analyzer/verilog/projs/top_mapped.proj
examples/rtl_analyzer/verilog/reports/
examples/rtl_analyzer/verilog/reports/top_area.rpt
examples/rtl_analyzer/verilog/reports/top_gtech_chk.rpt
examples/rtl_analyzer/verilog/reports/top_mapped_chk.rpt
examples/rtl_analyzer/verilog/reports/top_timing.rpt
examples/rtl_analyzer/verilog/scripts/
examples/rtl_analyzer/verilog/scripts/constraints.scr
examples/rtl_analyzer/verilog/scripts/gtech.scr
examples/rtl_analyzer/verilog/scripts/gtech_fast.scr
examples/rtl_analyzer/verilog/scripts/mapped.scr
examples/rtl_analyzer/verilog/scripts/mapped_fast.scr
examples/rtl_analyzer/verilog/scripts/recompile.scr
examples/rtl_analyzer/verilog/scripts/setup.scr
examples/rtl_analyzer/verilog/scripts/setup_fast.scr
examples/rtl_analyzer/verilog/scripts/top.scr
examples/rtl_analyzer/verilog/scripts/top_const.scr
examples/rtl_analyzer/verilog/scripts/top_fast.scr
examples/rtl_analyzer/verilog/unmapped/
examples/rtl_analyzer/verilog/unmapped/top_gtech.db
examples/rtl_analyzer/verilog/work_lib/
examples/rtl_analyzer/verilog/work_lib/addr_combo%verilog.syn
examples/rtl_analyzer/verilog/work_lib/addr_combo%verilog__verilog.syn
examples/rtl_analyzer/verilog/work_lib/ADDR_COMBO.mr
examples/rtl_analyzer/verilog/work_lib/addr_fsm%verilog.syn
examples/rtl_analyzer/verilog/work_lib/addr_fsm%verilog__verilog.syn
examples/rtl_analyzer/verilog/work_lib/ADDR_FSM.mr
examples/rtl_analyzer/verilog/work_lib/top%verilog.syn
examples/rtl_analyzer/verilog/work_lib/top%verilog__verilog.syn
examples/rtl_analyzer/verilog/work_lib/TOP.mr
examples/rtl_analyzer/vhdl/
examples/rtl_analyzer/vhdl/.synopsys_dc.setup
examples/rtl_analyzer/vhdl/clean
examples/rtl_analyzer/vhdl/gtech/
examples/rtl_analyzer/vhdl/gtech/addr_combo.ra
examples/rtl_analyzer/vhdl/gtech/addr_combo.vhd.bi
examples/rtl_analyzer/vhdl/gtech/addr_combo.vhd.id
examples/rtl_analyzer/vhdl/gtech/addr_combo_rtl.vhd.bi
examples/rtl_analyzer/vhdl/gtech/addr_combo_rtl.vhd.id
examples/rtl_analyzer/vhdl/gtech/addr_fsm.ra
examples/rtl_analyzer/vhdl/gtech/addr_fsm.vhd.bi
examples/rtl_analyzer/vhdl/gtech/addr_fsm.vhd.id
examples/rtl_analyzer/vhdl/gtech/addr_fsm_rtl.vhd.bi
examples/rtl_analyzer/vhdl/gtech/addr_fsm_rtl.vhd.id
examples/rtl_analyzer/vhdl/gtech/datapath_pack.vhd.bi
examples/rtl_analyzer/vhdl/gtech/datapath_pack.vhd.id
examples/rtl_analyzer/vhdl/gtech/datapath_pack_body.vhd.bi
examples/rtl_analyzer/vhdl/gtech/datapath_pack_body.vhd.id
examples/rtl_analyzer/vhdl/gtech/top.ra
examples/rtl_analyzer/vhdl/gtech/top.vhd.bi
examples/rtl_analyzer/vhdl/gtech/top.vhd.id
examples/rtl_analyzer/vhdl/gtech/top_rtl.vhd.bi
examples/rtl_analyzer/vhdl/gtech/top_rtl.vhd.id
examples/rtl_analyzer/vhdl/gtech_fast/
examples/rtl_analyzer/vhdl/hdl/
examples/rtl_analyzer/vhdl/hdl/addr_combo.vhd
examples/rtl_analyzer/vhdl/hdl/addr_combo_fast_rtl.vhd
examples/rtl_analyzer/vhdl/hdl/addr_combo_rtl.vhd
examples/rtl_analyzer/vhdl/hdl/addr_fsm.vhd
examples/rtl_analyzer/vhdl/hdl/addr_fsm_rtl.vhd
examples/rtl_analyzer/vhdl/hdl/datapath_pack.vhd
examples/rtl_analyzer/vhdl/hdl/datapath_pack_body.vhd
examples/rtl_analyzer/vhdl/hdl/top.vhd
examples/rtl_analyzer/vhdl/hdl/top_rtl.vhd
examples/rtl_analyzer/vhdl/init.proj
examples/rtl_analyzer/vhdl/libs/
examples/rtl_analyzer/vhdl/libs/class.db
examples/rtl_analyzer/vhdl/mapped/
examples/rtl_analyzer/vhdl/mapped/top_mapped.db
examples/rtl_analyzer/vhdl/projs/
examples/rtl_analyzer/vhdl/projs/top_cons.scr
examples/rtl_analyzer/vhdl/projs/top_gtech.proj
examples/rtl_analyzer/vhdl/projs/top_mapped.proj
examples/rtl_analyzer/vhdl/reports/
examples/rtl_analyzer/vhdl/reports/top_area.rpt
examples/rtl_analyzer/vhdl/reports/top_gtech_chk.rpt
examples/rtl_analyzer/vhdl/reports/top_mapped_chk.rpt
examples/rtl_analyzer/vhdl/reports/top_timing.rpt
examples/rtl_analyzer/vhdl/scripts/
examples/rtl_analyzer/vhdl/scripts/constraints.scr
examples/rtl_analyzer/vhdl/scripts/gtech.scr
examples/rtl_analyzer/vhdl/scripts/gtech_fast.scr
examples/rtl_analyzer/vhdl/scripts/mapped.scr
examples/rtl_analyzer/vhdl/scripts/mapped_fast.scr
examples/rtl_analyzer/vhdl/scripts/recompile.scr
examples/rtl_analyzer/vhdl/scripts/setup.scr
examples/rtl_analyzer/vhdl/scripts/setup_fast.scr
examples/rtl_analyzer/vhdl/scripts/top.scr
examples/rtl_analyzer/vhdl/scripts/top_const.scr
examples/rtl_analyzer/vhdl/scripts/top_fast.scr
examples/rtl_analyzer/vhdl/unmapped/
examples/rtl_analyzer/vhdl/unmapped/top_gtech.db
examples/rtl_analyzer/vhdl/work_lib/
examples/verilog/
examples/verilog/cla/
examples/verilog/cla/cla.scr
examples/verilog/cla/cla.v
examples/verilog/cnt-combin/
examples/verilog/cnt-combin/cnt-combin.scr
examples/verilog/cnt-combin/cnt-combin.v
examples/verilog/cnt-seq/
examples/verilog/cnt-seq/cnt-seq.scr
examples/verilog/cnt-seq/cnt-seq.v
examples/verilog/drink-cnt/
examples/verilog/drink-cnt/drink-cnt.scr
examples/verilog/drink-cnt/drink-cnt.v
examples/verilog/drink-st/
examples/verilog/drink-st/drink-st.scr
examples/verilog/drink-st/drink-st.v
examples/vhdl/
examples/vhdl/add-sub/
examples/vhdl/add-sub/addsub.scr
examples/vhdl/add-sub/addsub.vhd
examples/vhdl/cla/
examples/vhdl/cla/cla.scr
examples/vhdl/cla/cla.vhd
examples/vhdl/cla/command.log
examples/vhdl/cla/local-pack.vhd
examples/vhdl/cnt-combin/
examples/vhdl/cnt-combin/cnt-combin.scr
examples/vhdl/cnt-combin/cnt-combin.vhd
examples/vhdl/cnt-seq/
examples/vhdl/cnt-seq/cnt-seq.scr
examples/vhdl/cnt-seq/cnt-seq.vhd
examples/vhdl/drink-cnt/
examples/vhdl/drink-cnt/drink-cnt.scr
examples/vhdl/drink-cnt/drink-cnt.vhd
examples/vhdl/drink-st/
examples/vhdl/drink-st/drink-st.scr
examples/vhdl/drink-st/drink-st.vhd
examples/vhdl/mealy/
examples/vhdl/mealy/mealy.scr
examples/vhdl/mealy/mealy.vhd
examples/vhdl/moore/
examples/vhdl/moore/moore.scr
examples/vhdl/moore/moore.vhd
examples/vhdl/pla/
examples/vhdl/pla/local-pack.vhd
examples/vhdl/pla/pla.scr
examples/vhdl/pla/pla.vhd
examples/vhdl/ROM/
examples/vhdl/ROM/command.log
examples/vhdl/ROM/ROM.scr
examples/vhdl/ROM/ROM.vhd
examples/vhdl/s2p-count/
examples/vhdl/s2p-count/s2p-count.scr
examples/vhdl/s2p-count/s2p-count.vhd
examples/vhdl/s2p-count/types-pack.vhd
examples/vhdl/s2p-seq/
examples/vhdl/s2p-seq/s2p-seq.scr
examples/vhdl/s2p-seq/s2p-seq.vhd
examples/vhdl/s2p-seq/types-pack.vhd
examples/vhdl/smart-gen/
examples/vhdl/smart-gen/smart-gen.scr
examples/vhdl/smart-gen/smart-gen.vhd
examples/vhdl/wave-gen/
examples/vhdl/wave-gen/wave-gen.scr
examples/vhdl/wave-gen/wave-gen.vhd
guidelines/
guidelines/.synopsys_dc.setup
guidelines/scr/
guidelines/scr/adder16.scr
guidelines/scr/cascademod.scr
guidelines/scr/characterize.scr
guidelines/scr/comp16.scr
guidelines/scr/defaults.con
guidelines/scr/initial_compile.scr
guidelines/scr/mult16.scr
guidelines/scr/mult8.scr
guidelines/scr/muxmod.scr
guidelines/scr/pathseg.scr
guidelines/scr/read.scr
guidelines/scr/recompile.scr
guidelines/scr/report.scr
guidelines/scr/run.scr
guidelines/src/
guidelines/src/Adder16.v
guidelines/src/Adder8.v
guidelines/src/CascadeMod.v
guidelines/src/ChipLevel.v
guidelines/src/Comparator.v
guidelines/src/Counter.v
guidelines/src/def_macro.v
guidelines/src/Multiply16x16.v
guidelines/src/Multiply8x8.v
guidelines/src/MuxMod.v
guidelines/src/PathSegment.v
power_tutorial/
power_tutorial/binary/
power_tutorial/binary/db/
power_tutorial/binary/db/binary.compiled.db
power_tutorial/binary/db/binary.read.db
power_tutorial/binary/db/binary_gatesim.db
power_tutorial/binary/gatesim/
power_tutorial/binary/gatesim/.synopsys_dc.setup
power_tutorial/binary/gatesim/.synopsys_vss.setup
power_tutorial/binary/gatesim/binary.tv
power_tutorial/binary/gatesim/binary.vhd
power_tutorial/binary/gatesim/binary_gatesim.vhd
power_tutorial/binary/gatesim/binary_vss_toggle_count
power_tutorial/binary/gatesim/change_names.scr
power_tutorial/binary/gatesim/constants.vhd
power_tutorial/binary/gatesim/gatesim.scr
power_tutorial/binary/gatesim/gatesyn.scr
power_tutorial/binary/gatesim/gatesyn.scr.out
power_tutorial/binary/gatesim/report_power.final.binary
power_tutorial/binary/gatesim/report_power.final.cell.binary
power_tutorial/binary/gatesim/report_power.final.net.binary
power_tutorial/binary/gatesim/report_power.scr
power_tutorial/binary/gatesim/run.gatesim.scr
power_tutorial/binary/gatesim/set_switching_activity.gatesim.scr
power_tutorial/binary/gatesim/set_switching_activity.input_port.scr
power_tutorial/binary/gatesim/sim.trace.scr
power_tutorial/binary/gatesim/tb_binary.vhd
power_tutorial/binary/verilog/
power_tutorial/binary/verilog/.synopsys_dc.setup
power_tutorial/binary/verilog/.synopsys_vss.setup
power_tutorial/binary/verilog/binary.v
power_tutorial/binary/vhdl/
power_tutorial/binary/vhdl/.synopsys_dc.setup
power_tutorial/binary/vhdl/.synopsys_vss.setup
power_tutorial/binary/vhdl/binary.tv
power_tutorial/binary/vhdl/binary.vhd
power_tutorial/binary/vhdl/constants.vhd
power_tutorial/binary/vhdl/input.list
power_tutorial/binary/vhdl/interface.out
power_tutorial/binary/vhdl/interface.scr
power_tutorial/binary/vhdl/interface.tv.scr
power_tutorial/binary/vhdl/port.tog
power_tutorial/binary/vhdl/quick_map.scr
power_tutorial/binary/vhdl/report_power.binary
power_tutorial/binary/vhdl/report_power.cell
power_tutorial/binary/vhdl/report_power.net
power_tutorial/binary/vhdl/run.sim.scr
power_tutorial/binary/vhdl/run.syn.scr
power_tutorial/binary/vhdl/seq_output.ssa
power_tutorial/binary/vhdl/set_switching_activity.scr
power_tutorial/binary/vhdl/set_switching_activity.tv.scr
power_tutorial/binary/vhdl/simulate_binary_rtl
power_tutorial/binary/vhdl/tb_binary.vhd
power_tutorial/lib/
power_tutorial/lib/.synopsys_dc.setup
power_tutorial/lib/.synopsys_vss.setup
power_tutorial/lib/build_vhdl_ftgs_lib.scr
power_tutorial/lib/class.db
power_tutorial/lib/class.lib
power_tutorial/lib/class_components.vhd
power_tutorial/lib/class_FTGS.vhd.E
power_tutorial/lib/class_sim/
power_tutorial/onehot/
power_tutorial/onehot/db/
power_tutorial/onehot/db/onehot.compiled.db
power_tutorial/onehot/db/onehot.read.db
power_tutorial/onehot/verilog/
power_tutorial/onehot/verilog/.synopsys_dc.setup
power_tutorial/onehot/verilog/.synopsys_vss.setup
power_tutorial/onehot/verilog/onehot.v
power_tutorial/onehot/vhdl/
power_tutorial/onehot/vhdl/.synopsys_dc.setup
power_tutorial/onehot/vhdl/.synopsys_vss.setup
power_tutorial/onehot/vhdl/constants.vhd
power_tutorial/onehot/vhdl/input.list
power_tutorial/onehot/vhdl/interface.out
power_tutorial/onehot/vhdl/onehot.tv
power_tutorial/onehot/vhdl/onehot.vhd
power_tutorial/onehot/vhdl/port.tog
power_tutorial/onehot/vhdl/quick_map.scr
power_tutorial/onehot/vhdl/report_power.cell
power_tutorial/onehot/vhdl/report_power.net
power_tutorial/onehot/vhdl/report_power.onehot
power_tutorial/onehot/vhdl/run.sim.scr
power_tutorial/onehot/vhdl/run.syn.scr
power_tutorial/onehot/vhdl/seq_output.ssa
power_tutorial/onehot/vhdl/set_switching_activity.scr
power_tutorial/onehot/vhdl/set_switching_activity.tv.scr
power_tutorial/onehot/vhdl/simulate_onehot
power_tutorial/onehot/vhdl/tb_onehot.vhd
power_tutorial/ripple/
power_tutorial/ripple/db/
power_tutorial/ripple/db/ripple.compiled.db
power_tutorial/ripple/db/ripple.read.db
power_tutorial/ripple/verilog/
power_tutorial/ripple/verilog/.synopsys_dc.setup
power_tutorial/ripple/verilog/.synopsys_vss.setup
power_tutorial/ripple/verilog/ripple.v
power_tutorial/ripple/vhdl/
power_tutorial/ripple/vhdl/.synopsys_dc.setup
power_tutorial/ripple/vhdl/.synopsys_vss.setup
power_tutorial/ripple/vhdl/constants.vhd
power_tutorial/ripple/vhdl/input.list
power_tutorial/ripple/vhdl/interface.out
power_tutorial/ripple/vhdl/port.tog
power_tutorial/ripple/vhdl/quick_map.scr
power_tutorial/ripple/vhdl/report_power.cell
power_tutorial/ripple/vhdl/report_power.net
power_tutorial/ripple/vhdl/report_power.ripple
power_tutorial/ripple/vhdl/ripple.tv
power_tutorial/ripple/vhdl/ripple.vhd
power_tutorial/ripple/vhdl/run.sim.scr
power_tutorial/ripple/vhdl/run.syn.scr
power_tutorial/ripple/vhdl/seq_output.ssa
power_tutorial/ripple/vhdl/set_switching_activity.scr
power_tutorial/ripple/vhdl/set_switching_activity.tv.scr
power_tutorial/ripple/vhdl/simulate_ripple
power_tutorial/ripple/vhdl/tb_ripple.vhd
power_tutorial/work/
power_tutorial/work/sparc/
scan_tutorial/
scan_tutorial/.answers1/
scan_tutorial/.answers1/CLOCK_GEN.v
scan_tutorial/.answers1/CLOCK_GEN.vhd
scan_tutorial/.answers1/COMPUTE_BLOCK.v
scan_tutorial/.answers1/COMPUTE_BLOCK.vhd
scan_tutorial/.answers2/
scan_tutorial/.answers2/COMPUTE_BLOCK.v
scan_tutorial/.answers2/COMPUTE_BLOCK.vhd
scan_tutorial/.answers2/TOP.v
scan_tutorial/.answers2/TOP.vhd
scan_tutorial/.script_verilog
scan_tutorial/.script_vhdl
scan_tutorial/.synopsys_dc.setup
scan_tutorial/verilog/
scan_tutorial/verilog/ALARM_BLOCK.v
scan_tutorial/verilog/ALARM_SM_2.v
scan_tutorial/verilog/CLOCK_GEN.v
scan_tutorial/verilog/COMPARATOR.v
scan_tutorial/verilog/COMPUTE_BLOCK.v
scan_tutorial/verilog/CONVERTOR.pla
scan_tutorial/verilog/CONVERTOR_CKT.v
scan_tutorial/verilog/TIME_BLOCK.v
scan_tutorial/verilog/TOP.v
scan_tutorial/vhdl/
scan_tutorial/vhdl/ALARM_BLOCK.vhd
scan_tutorial/vhdl/ALARM_SM_2.vhd
scan_tutorial/vhdl/CLOCK_GEN.vhd
scan_tutorial/vhdl/COMPARATOR.vhd
scan_tutorial/vhdl/COMPUTE_BLOCK.vhd
scan_tutorial/vhdl/CONVERTOR.pla
scan_tutorial/vhdl/CONVERTOR_CKT.vhd
scan_tutorial/vhdl/TIME_BLOCK.vhd
scan_tutorial/vhdl/TOP.vhd
test_tutorial/
test_tutorial/.synopsys_dc.setup
test_tutorial/appendix/
test_tutorial/appendix/chapter2/
test_tutorial/appendix/chapter2/CLOCK_GEN.v
test_tutorial/appendix/chapter2/CLOCK_GEN.vhd
test_tutorial/appendix/chapter2/COMPUTE_BLOCK.v
test_tutorial/appendix/chapter2/COMPUTE_BLOCK.vhd
test_tutorial/appendix/chapter2/verilog.scr
test_tutorial/appendix/chapter2/vhdl.scr
test_tutorial/appendix/chapter3/
test_tutorial/appendix/chapter3/COMPUTE_BLOCK.v
test_tutorial/appendix/chapter3/COMPUTE_BLOCK.vhd
test_tutorial/appendix/chapter3/TOP.v
test_tutorial/appendix/chapter3/TOP.vhd
test_tutorial/appendix/chapter3/verilog.scr
test_tutorial/appendix/chapter3/vhdl.scr
test_tutorial/appendix/chapter4/
test_tutorial/appendix/chapter4/fnc.sdf
test_tutorial/appendix/chapter4/run.inc
test_tutorial/appendix/chapter4/run.scr
test_tutorial/appendix/chapter4/sdf.scr
test_tutorial/appendix/chapter4/tb_alarm.v
test_tutorial/appendix/chapter4/tb_alarm.vhd
test_tutorial/appendix/chapter4/verilog.csh
test_tutorial/appendix/chapter4/verilog2tds.awk
test_tutorial/appendix/chapter4/vhdl.csh
test_tutorial/appendix/chapter5/
test_tutorial/appendix/chapter5/run.scr
test_tutorial/library/
test_tutorial/library/class.db
test_tutorial/library/class.sdb
test_tutorial/library/verilog/
test_tutorial/library/verilog/class.v
test_tutorial/verilog/
test_tutorial/verilog/ALARM_BLOCK.v
test_tutorial/verilog/ALARM_SM_2.v
test_tutorial/verilog/CLOCK_GEN.v
test_tutorial/verilog/COMPARATOR.v
test_tutorial/verilog/COMPUTE_BLOCK.db
test_tutorial/verilog/COMPUTE_BLOCK.v
test_tutorial/verilog/CONVERTOR.pla
test_tutorial/verilog/CONVERTOR_CKT.v
test_tutorial/verilog/read.scr
test_tutorial/verilog/TIME_BLOCK.v
test_tutorial/verilog/TOP.v
test_tutorial/vhdl/
test_tutorial/vhdl/ALARM_BLOCK.vhd
test_tutorial/vhdl/ALARM_SM_2.vhd
test_tutorial/vhdl/CLOCK_GEN.vhd
test_tutorial/vhdl/COMPARATOR.vhd
test_tutorial/vhdl/COMPUTE_BLOCK.db
test_tutorial/vhdl/COMPUTE_BLOCK.vhd
test_tutorial/vhdl/CONVERTOR.pla
test_tutorial/vhdl/CONVERTOR_CKT.vhd
test_tutorial/vhdl/read.scr
test_tutorial/vhdl/TIME_BLOCK.vhd
test_tutorial/vhdl/TOP.vhd
tutorial/
tutorial/.synopsys_dc.setup
tutorial/.synopsys_dc.setup1
tutorial/.synopsys_dcsh.setup
tutorial/.synopsys_dctcl.setup
tutorial/appendix_A/
tutorial/appendix_A/analyzres.script
tutorial/appendix_A/analyzres.tcl
tutorial/appendix_A/cmpldes1.script
tutorial/appendix_A/cmpldes1.tcl
tutorial/appendix_A/cmpldes2.script
tutorial/appendix_A/cmpldes2.tcl
tutorial/appendix_A/optgoals.script
tutorial/appendix_A/optgoals.tcl
tutorial/appendix_A/setenv.script
tutorial/appendix_A/setenv.tcl
tutorial/db/
tutorial/db/ALARM_BLOCK.db
tutorial/db/ALARM_COUNTER.db
tutorial/db/ALARM_SM_2.db
tutorial/db/ALARM_STATE_MACHINE.db
tutorial/db/COMPARATOR.db
tutorial/db/CONVERTOR.pla
tutorial/db/CONVERTOR_CKT.db
tutorial/db/HOURS_FILTER.db
tutorial/db/MUX.db
tutorial/db/TIME_BLOCK.db
tutorial/db/TIME_COUNTER.db
tutorial/db/TIME_STATE_MACHINE.db
tutorial/db/TOP.db
tutorial/verilog/
tutorial/verilog/ALARM_BLOCK.v
tutorial/verilog/ALARM_COUNTER.v
tutorial/verilog/ALARM_SM_2.v
tutorial/verilog/ALARM_STATE_MACHINE.v
tutorial/verilog/COMPARATOR.v
tutorial/verilog/CONVERTOR.pla
tutorial/verilog/CONVERTOR_CKT.v
tutorial/verilog/HOURS_FILTER.v
tutorial/verilog/MUX.v
tutorial/verilog/TIME_BLOCK.v
tutorial/verilog/TIME_COUNTER.v
tutorial/verilog/TIME_STATE_MACHINE.v
tutorial/verilog/TOP.v
tutorial/vhdl/
tutorial/vhdl/ALARM_BLOCK.vhd
tutorial/vhdl/ALARM_COUNTER.vhd
tutorial/vhdl/ALARM_SM_2.vhd
tutorial/vhdl/ALARM_STATE_MACHINE.vhd
tutorial/vhdl/COMPARATOR.vhd
tutorial/vhdl/CONVERTOR.pla
tutorial/vhdl/CONVERTOR_CKT.vhd
tutorial/vhdl/HOURS_FILTER.vhd
tutorial/vhdl/MUX.vhd
tutorial/vhdl/synopsys.vhd
tutorial/vhdl/TIME_BLOCK.vhd
tutorial/vhdl/TIME_COUNTER.vhd
tutorial/vhdl/TIME_STATE_MACHINE.vhd
tutorial/vhdl/TOP.vhd
tutorial/work/