文件名称:gate
介绍说明－－下载内容均来自于网络，请自行研究使用
verilog中调用门级电路的实验程序，实现了门级舰模
(系统自动生成,下载前可以参看下载内容)
下载文件列表
压缩包 : 55593406gate.rar 列表 gate\gate.qpf gate\gate.qsf gate\db\gate.db_info gate\db\gate.cmp.rdb gate\db\gate.tan.qmsg gate\db\gate.sld_design_entry.sci gate\db\gate.pre_map.cdb gate\db\gate.rtlv.hdb gate\db\gate.map.qmsg gate\db\gate.(0).cnf.cdb gate\db\gate.eco.cdb gate\db\gate_cmp.qrpt gate\db\gate.cbx.xml gate\db\gate.hif gate\db\gate.map.hdb gate\db\gate.rtlv_sg_swap.cdb gate\db\gate.fit.qmsg gate\db\gate.(0).cnf.hdb gate\db\gate.eda.qmsg gate\db\gate.pre_map.hdb gate\db\gate.sgdiff.cdb gate\db\gate.sim.qmsg gate\db\gate.sim.vwf gate\db\gate.sim.rdb gate\db\gate.map.cdb gate\db\gate.sim.hdb gate\db\gate.asm.qmsg gate\db\gate.rtlv_sg.cdb gate\db\gate.sgdiff.hdb gate\db\gate.sld_design_entry_dsc.sci gate\db\gate.hier_info gate\db\gate.eds_overflow gate\db\gate_sim.qrpt gate\db\gate.cmp0.ddb gate\db\gate.cmp.cdb gate\db\gate.signalprobe.cdb gate\db\gate.psp gate\db\gate.cmp.hdb gate\db\gate.cmp.tdb gate\db\gate.syn_hier_info gate\gate.map.rpt gate\gate.flow.rpt gate\gate.map.summary gate\gate.map.eqn gate\gate.fit.eqn gate\gate.pin gate\gate.fit.rpt gate\gate.fit.summary gate\gate.sof gate\gate.pof gate\gate.asm.rpt gate\gate.tan.summary gate\gate.tan.rpt gate\gate.done gate\flop.bsf gate\gate.bdf gate\gate.vwf gate\gate.sim.rpt gate\gate.vt gate\work\_info gate\work\flop_vlg_sample_tst\_primary.vhd gate\work\flop_vlg_sample_tst\_primary.dat gate\work\flop_vlg_check_tst\_primary.vhd gate\work\flop_vlg_check_tst\_primary.dat gate\work\flop_vlg_vec_tst\_primary.vhd gate\work\flop_vlg_vec_tst\_primary.dat gate\work\flop\_primary.vhd gate\work\flop\_primary.dat gate\work\zz\work__info gate\work\zz\work_flop_fast.asm gate\work\zz\work_flop_fast.dt2 gate\work\zz\_deps gate\work\_opt\work__info gate\work\_opt\_deps gate\work\_opt\work_flop_vlg_check_tst_fast.asm gate\work\_opt\work_flop_vlg_check_tst_fast.dt2 gate\work\_opt\work_flop_vlg_sample_tst_fast.asm gate\work\_opt\work_flop_vlg_sample_tst_fast.dt2 gate\work\_opt\work_flop_fast.asm gate\work\_opt\work_flop_fast.dt2 gate\work\_opt\work_flop_vlg_vec_tst_fast.asm gate\work\_opt\work_flop_vlg_vec_tst_fast.dt2 gate\simulation\modelsim\gate.vt gate\simulation\modelsim\gate_modelsim.xrf gate\simulation\modelsim\gate.vo gate\simulation\modelsim\gate_v.sdo gate\gate.eda.rpt gate\quartus_nativelink_simulation.log gate\vsim.wlf gate\testben.mpf gate\Waveform1.vwf gate\Waveform1.vt gate\Waveform1.v gate\testben.cr.mti gate\g\work\_info gate\g\work\flop_vlg_sample_tst\_primary.vhd gate\g\work\flop_vlg_sample_tst\_primary.dat gate\g\work\flop_vlg_check_tst\_primary.vhd gate\g\work\flop_vlg_check_tst\_primary.dat gate\g\work\flop_vlg_vec_tst\_primary.vhd gate\g\work\flop_vlg_vec_tst\_primary.dat gate\g\work\_opt\work__info gate\g\work\_opt\work_flop_vlg_sample_tst_fast.asm gate\g\work\_opt\work_flop_vlg_sample_tst_fast.dt2 gate\g\work\_opt\_deps gate\g\work\_opt1\work__info gate\g\work\_opt1\work_flop_vlg_check_tst_fast.asm gate\g\work\_opt1\work_flop_vlg_check_tst_fast.dt2 gate\g\work\_opt1\_deps gate\g\vsim.wlf gate\g\ddd.mpf gate\gate.qws gate\flop.v gate\cmp_state.ini gate\g\work\_temp gate\g\work\flop_vlg_sample_tst gate\g\work\flop_vlg_check_tst gate\g\work\flop_vlg_vec_tst gate\g\work\_opt gate\g\work\_opt1 gate\work\_temp gate\work\flop_vlg_sample_tst gate\work\flop_vlg_check_tst gate\work\flop_vlg_vec_tst gate\work\flop gate\work\zz gate\work\_opt gate\simulation\modelsim gate\g\work gate\db gate\work gate\simulation gate\g gate