文件名称:Design of a Low-Power CMOS LVDS I/O Interface Circuit
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Abstract: The paper presents the design and implementation of LVDS (low-voltage differential signaling) receiver circuit, fully
compatible with LVDS standard. The proposed circuit is composed of the telescopic amplifier and the comparator with internal
hysteresis. The receiver supports 3.5 Gbps data rate with 7.4 mA current at 1.8 V supply according to post-layout circuit simulations.
The circuit has the power consumption of 13.1 MW. Comparing with the conventional circuit, the circuit is achieved to reduce the
power consumption by 19.1% and the data rate by 14.3%. The validity and effectiveness of the proposed circuit are verified through the
circuit simulation with Samsung 0.18 μm CMOS (complementary metal-oxide-semiconductor) standard technology under the 1.8 V
supply voltage.
compatible with LVDS standard. The proposed circuit is composed of the telescopic amplifier and the comparator with internal
hysteresis. The receiver supports 3.5 Gbps data rate with 7.4 mA current at 1.8 V supply according to post-layout circuit simulations.
The circuit has the power consumption of 13.1 MW. Comparing with the conventional circuit, the circuit is achieved to reduce the
power consumption by 19.1% and the data rate by 14.3%. The validity and effectiveness of the proposed circuit are verified through the
circuit simulation with Samsung 0.18 μm CMOS (complementary metal-oxide-semiconductor) standard technology under the 1.8 V
supply voltage.
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