文件名称:i2c

  • 所属分类:
  • 其它资源
  • 资源属性:
  • [C/C++] [源码]
  • 上传时间:
  • 2008-10-13
  • 文件大小:
  • 486.44kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 邵*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!
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opencores上的源码,帮大家搞下来了,希望对大家有帮助 ,
(系统自动生成,下载前可以参看下载内容)

下载文件列表

压缩包 : 41695059i2c.rar 列表
rtl\vhdl\readme
doc\src\I2C_specs.doc
sim\i2c_verilog\run\ncverilog.log
software\include\oc_i2c_master.h
documentation\CVS\Entries
sim\i2c_verilog\run\INCA_libs\CVS\Entries
sim\i2c_verilog\run\waves\CVS\Entries
software\drivers\CVS\Entries
verilog\CVS\Entries
vhdl\CVS\Entries
sim\i2c_verilog\CVS\Entries
bench\CVS\Entries
sim\CVS\Entries
rtl\CVS\Entries
software\CVS\Entries
software\include\CVS\Entries
doc\src\CVS\Entries
doc\CVS\Entries
CVS\Entries
sim\i2c_verilog\run\CVS\Entries
bench\verilog\CVS\Entries
rtl\verilog\CVS\Entries
rtl\vhdl\CVS\Entries
CVS\Repository
doc\CVS\Repository
rtl\CVS\Repository
sim\CVS\Repository
vhdl\CVS\Repository
bench\CVS\Repository
doc\src\CVS\Repository
verilog\CVS\Repository
rtl\vhdl\CVS\Repository
software\CVS\Repository
rtl\verilog\CVS\Repository
bench\verilog\CVS\Repository
documentation\CVS\Repository
sim\i2c_verilog\CVS\Repository
software\drivers\CVS\Repository
software\include\CVS\Repository
sim\i2c_verilog\run\CVS\Repository
sim\i2c_verilog\run\waves\CVS\Repository
sim\i2c_verilog\run\INCA_libs\CVS\Repository
bench\CVS\Root
bench\verilog\CVS\Root
CVS\Root
doc\CVS\Root
doc\src\CVS\Root
documentation\CVS\Root
rtl\CVS\Root
rtl\verilog\CVS\Root
rtl\vhdl\CVS\Root
sim\CVS\Root
sim\i2c_verilog\CVS\Root
sim\i2c_verilog\run\CVS\Root
sim\i2c_verilog\run\INCA_libs\CVS\Root
sim\i2c_verilog\run\waves\CVS\Root
software\CVS\Root
software\drivers\CVS\Root
software\include\CVS\Root
verilog\CVS\Root
vhdl\CVS\Root
sim\i2c_verilog\run\run
sim\i2c_verilog\run\ncverilog.key
doc\i2c_specs.pdf
rtl\verilog\i2c_master_bit_ctrl.v
rtl\verilog\i2c_master_byte_ctrl.v
rtl\verilog\i2c_master_defines.v
rtl\verilog\i2c_master_top.v
bench\verilog\i2c_slave_model.v
bench\verilog\spi_slave_model.v
rtl\verilog\timescale.v
bench\verilog\tst_bench_top.v
bench\verilog\wb_master_model.v
sim\i2c_verilog\run\bench.vcd
rtl\vhdl\I2C.VHD
rtl\vhdl\i2c_master_bit_ctrl.vhd
rtl\vhdl\i2c_master_byte_ctrl.vhd
rtl\vhdl\i2c_master_top.vhd
rtl\vhdl\tst_ds1621.vhd
sim\i2c_verilog\run\INCA_libs\CVS
sim\i2c_verilog\run\waves\CVS
sim\i2c_verilog\run\CVS
sim\i2c_verilog\run\INCA_libs
sim\i2c_verilog\run\waves
bench\verilog\CVS
doc\src\CVS
rtl\verilog\CVS
rtl\vhdl\CVS
sim\i2c_verilog\CVS
software\drivers\CVS
software\include\CVS
sim\i2c_verilog\run
bench\CVS
doc\CVS
documentation\CVS
rtl\CVS
sim\CVS
software\CVS
verilog\CVS
vhdl\CVS
software\drivers
sim\i2c_verilog
software\include
doc\src
bench\verilog
rtl\verilog
rtl\vhdl
bench
CVS
doc
documentation
rtl
sim
software
verilog
vhdl

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