文件名称:cordic

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [Windows] [程序]
  • 上传时间:
  • 2018-08-26
  • 文件大小:
  • 95kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 涛201****
  • 相关连接:
  • 下载说明:
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介绍说明--下载内容均来自于网络,请自行研究使用

基于verilog HDL的cordic算法FPGA实现。省去繁琐的乘法开方计算。IDE为vivado 2014( U57FA u4E8Everilog HDL u7684cordic u7B97 u6CD5FPGA u5B9E u73B0 u3002 u7B1 u53BB u7E1 u7410 u7684 u4E58 u6CD5 u5F00 u65B9 u8BA1 u7B97 u300BIDE u4E3Avivado 2014)
(系统自动生成,下载前可以参看下载内容)

下载文件列表

cordic

cordic\project_1.cache

cordic\project_1.cache\compile_simlib

cordic\project_1.cache\wt

cordic\project_1.cache\wt\synthesis.wdf

cordic\project_1.cache\wt\webtalk_pa.xml

cordic\project_1.cache\wt\xsim.wdf

cordic\project_1.sim

cordic\project_1.sim\sim_1

cordic\project_1.sim\sim_1\behav

cordic\project_1.sim\sim_1\behav\.Xil

cordic\project_1.sim\sim_1\behav\.Xil\Webtalk-4444-Y3IPYJD01HWTT7R

cordic\project_1.sim\sim_1\behav\.Xil\Webtalk-4444-Y3IPYJD01HWTT7R\webtalk

cordic\project_1.sim\sim_1\behav\.Xil\Webtalk-4992-Y3IPYJD01HWTT7R

cordic\project_1.sim\sim_1\behav\.Xil\Webtalk-4992-Y3IPYJD01HWTT7R\webtalk

cordic\project_1.sim\sim_1\behav\compile.bat

cordic\project_1.sim\sim_1\behav\compile.log

cordic\project_1.sim\sim_1\behav\cordic_vlg_tst.tcl

cordic\project_1.sim\sim_1\behav\cordic_vlg_tst_behav.wdb

cordic\project_1.sim\sim_1\behav\cordic_vlg_tst_vlog.prj

cordic\project_1.sim\sim_1\behav\elaborate.bat

cordic\project_1.sim\sim_1\behav\elaborate.log

cordic\project_1.sim\sim_1\behav\glbl.v

cordic\project_1.sim\sim_1\behav\simulate.bat

cordic\project_1.sim\sim_1\behav\simulate.log

cordic\project_1.sim\sim_1\behav\webtalk.jou

cordic\project_1.sim\sim_1\behav\webtalk.log

cordic\project_1.sim\sim_1\behav\webtalk_4444.backup.jou

cordic\project_1.sim\sim_1\behav\webtalk_4444.backup.log

cordic\project_1.sim\sim_1\behav\xelab.pb

cordic\project_1.sim\sim_1\behav\xsim.dir

cordic\project_1.sim\sim_1\behav\xsim.dir\cordic_vlg_tst_behav

cordic\project_1.sim\sim_1\behav\xsim.dir\cordic_vlg_tst_behav\Compile_Options.txt

cordic\project_1.sim\sim_1\behav\xsim.dir\cordic_vlg_tst_behav\webtalk

cordic\project_1.sim\sim_1\behav\xsim.dir\cordic_vlg_tst_behav\webtalk\.xsim_webtallk.info

cordic\project_1.sim\sim_1\behav\xsim.dir\cordic_vlg_tst_behav\webtalk\usage_statistics_ext_xsim.html

cordic\project_1.sim\sim_1\behav\xsim.dir\cordic_vlg_tst_behav\webtalk\usage_statistics_ext_xsim.xml

cordic\project_1.sim\sim_1\behav\xsim.dir\cordic_vlg_tst_behav\xsim.dbg

cordic\project_1.sim\sim_1\behav\xsim.dir\cordic_vlg_tst_behav\xsim.mem

cordic\project_1.sim\sim_1\behav\xsim.dir\cordic_vlg_tst_behav\xsim.reloc

cordic\project_1.sim\sim_1\behav\xsim.dir\cordic_vlg_tst_behav\xsim.rtti

cordic\project_1.sim\sim_1\behav\xsim.dir\cordic_vlg_tst_behav\xsim.svtype

cordic\project_1.sim\sim_1\behav\xsim.dir\cordic_vlg_tst_behav\xsim.type

cordic\project_1.sim\sim_1\behav\xsim.dir\cordic_vlg_tst_behav\xsim.xdbg

cordic\project_1.sim\sim_1\behav\xsim.dir\cordic_vlg_tst_behav\xsimcrash.log

cordic\project_1.sim\sim_1\behav\xsim.dir\cordic_vlg_tst_behav\xsimk.exe

cordic\project_1.sim\sim_1\behav\xsim.dir\cordic_vlg_tst_behav\xsimkernel.log

cordic\project_1.sim\sim_1\behav\xsim.dir\xil_defaultlib

cordic\project_1.sim\sim_1\behav\xsim.dir\xil_defaultlib\cordic.sdb

cordic\project_1.sim\sim_1\behav\xsim.dir\xil_defaultlib\cordic_vlg_tst.sdb

cordic\project_1.sim\sim_1\behav\xsim.dir\xil_defaultlib\glbl.sdb

cordic\project_1.sim\sim_1\behav\xsim.dir\xsim.svtype

cordic\project_1.sim\sim_1\behav\xvlog.pb

cordic\project_1.srcs

cordic\project_1.srcs\sim_1

cordic\project_1.srcs\sim_1\new

cordic\project_1.srcs\sim_1\new\cordic_vlg_tst.v

cordic\project_1.srcs\sources_1

cordic\project_1.srcs\sources_1\new

cordic\project_1.srcs\sources_1\new\cordic.v

cordic\project_1.xpr

cordic\vivado.jou

cordic\vivado.log

cordic\vivado_4892.backup.jou

cordic\vivado_4892.backup.log

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