文件名称:fpga_slavefifo2b_verilog

  • 所属分类:
  • 串口编程
  • 资源属性:
  • 上传时间:
  • 2018-04-14
  • 文件大小:
  • 2.4mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • zes****
  • 相关连接:
  • 下载说明:
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介绍说明--下载内容均来自于网络,请自行研究使用

fpga控制USB接口数据收发,包含verilog
仿真代码和调试工程(fpga control usb3.0, modelsim simulation, verilog language)
相关搜索: usb3
fpga
verilog

(系统自动生成,下载前可以参看下载内容)

下载文件列表

文件名大小更新时间
fpga_slavefifo2b_verilog 0 2017-10-20
fpga_slavefifo2b_verilog\.Xil 0 2017-10-20
fpga_slavefifo2b_verilog\.Xil\PlanAhead-23372-LAPWIN7-KEAJ 0 2017-10-20
fpga_slavefifo2b_verilog\.Xil\PlanAhead-23372-LAPWIN7-KEAJ\ngc2edif 0 2017-10-20
fpga_slavefifo2b_verilog\.Xil\PlanAhead-23372-LAPWIN7-KEAJ\ngc2edif\ngc2edif.log 442 2014-08-01
fpga_slavefifo2b_verilog\.Xil\PlanAhead-23372-LAPWIN7-KEAJ\ngc2edif\slaveFIFO2b_fpga_top.edif 763226 2014-08-01
fpga_slavefifo2b_verilog\.Xil\PlanAhead-23372-LAPWIN7-KEAJ\ngc2edif\_xmsgs 0 2017-10-20
fpga_slavefifo2b_verilog\.Xil\PlanAhead-23372-LAPWIN7-KEAJ\ngc2edif\_xmsgs\ngc2edif.xmsgs 532 2014-08-01
fpga_slavefifo2b_verilog\clk_wiz_v3_2_2.v 5569 2013-02-18
fpga_slavefifo2b_verilog\fifo.v 3951 2013-02-13
fpga_slavefifo2b_verilog\fuse.log 2731 2017-10-19
fpga_slavefifo2b_verilog\fuse.xmsgs 549 2017-10-19
fpga_slavefifo2b_verilog\fuseRelaunch.cmd 280 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir 0 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\coregen.cgp 237 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\coregen.log 2705 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\create_icon_v1.tcl 1334 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\create_ila_v1.tcl 1337 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\create_pll50mi_100mo.tcl 1262 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\create_vio_v1.tcl 1327 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\edit_icon_v1.tcl 1123 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\edit_ila_v1.tcl 1122 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\icon_v1.asy 286 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\icon_v1.constraints 0 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\icon_v1.constraints\icon_v1.ucf 375 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\icon_v1.constraints\icon_v1.xdc 793 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\icon_v1.gise 1261 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\icon_v1.ncf 0 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\icon_v1.ngc 41535 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\icon_v1.sym 888 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\icon_v1.ucf 375 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\icon_v1.v 919 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\icon_v1.veo 1115 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\icon_v1.xco 1659 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\icon_v1.xdc 793 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\icon_v1.xise 36157 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\icon_v1_flist.txt 315 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\icon_v1_readme.txt 1241 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\icon_v1_xmdf.tcl 3188 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\ila_v1.asy 345 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\ila_v1.cdc 4644 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\ila_v1.constraints 0 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\ila_v1.constraints\ila_v1.ucf 412 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\ila_v1.constraints\ila_v1.xdc 477 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\ila_v1.gise 1258 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\ila_v1.ncf 0 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\ila_v1.ngc 389229 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\ila_v1.sym 1040 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\ila_v1.ucf 412 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\ila_v1.v 931 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\ila_v1.veo 1124 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\ila_v1.xco 4384 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\ila_v1.xdc 477 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\ila_v1.xise 36146 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\ila_v1_flist.txt 321 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\ila_v1_readme.txt 1372 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\ila_v1_xmdf.tcl 3168 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo 0 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo.asy 447 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo.gise 1279 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo.ncf 2617 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo.sym 1261 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo.ucf 2615 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo.v 7071 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo.veo 3676 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo.xco 8228 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo.xdc 3058 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo.xise 4841 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\clk_wiz_v3_6_readme.txt 6131 2013-10-14
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\doc 0 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\doc\clk_wiz_v3_6_readme.txt 6131 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\doc\clk_wiz_v3_6_vinfo.html 6789 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\doc\pg065_clk_wiz.pdf 42657 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\example_design 0 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\example_design\pll50mi_100mo_exdes.ucf 2647 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\example_design\pll50mi_100mo_exdes.v 5082 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\example_design\pll50mi_100mo_exdes.xdc 3163 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\implement 0 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\implement\implement.bat 3685 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\implement\implement.sh 3564 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\implement\planAhead_ise.bat 2695 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\implement\planAhead_ise.sh 2603 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\implement\planAhead_ise.tcl 3115 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\implement\planAhead_rdn.bat 2690 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\implement\planAhead_rdn.sh 2595 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\implement\planAhead_rdn.tcl 3249 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\implement\xst.prj 90 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\implement\xst.scr 182 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\simulation 0 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\simulation\functional 0 2017-10-20
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\simulation\functional\simcmds.tcl 149 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\simulation\functional\simulate_isim.bat 2792 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\simulation\functional\simulate_isim.sh 2675 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\simulation\functional\simulate_mti.bat 2779 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\simulation\functional\simulate_mti.do 2702 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\simulation\functional\simulate_mti.sh 2649 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\simulation\functional\simulate_ncsim.sh 2780 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\simulation\functional\simulate_vcs.sh 2920 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\simulation\functional\ucli_commands.key 104 2017-10-19
fpga_slavefifo2b_verilog\ipcore_dir\pll50mi_100mo\simulation\functional\vcs_session.tcl 1109 2017-10-19

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