文件名称:one_1bit

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • 上传时间:
  • 2018-04-02
  • 文件大小:
  • 34.83mb
  • 下载次数:
  • 0次
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利用xilinx公司开发的vivado平台,实现调用1bitpwm信号实现下变频的功能(Using the vivado platform developed by Xilinx, we can realize the function of calling down the 1bitpwm signal to realize the down conversion.)
相关搜索: vivado

(系统自动生成,下载前可以参看下载内容)

下载文件列表

文件名大小更新时间
one_1bit\one_1bit.cache\ip\2017.4\240847cbae43d9a9\240847cbae43d9a9.xci 12772 2018-03-28
one_1bit\one_1bit.cache\ip\2017.4\240847cbae43d9a9\rom1.dcp 101884 2018-03-28
one_1bit\one_1bit.cache\ip\2017.4\240847cbae43d9a9\rom1_sim_netlist.v 172592 2018-03-28
one_1bit\one_1bit.cache\ip\2017.4\240847cbae43d9a9\rom1_sim_netlist.vhdl 195431 2018-03-28
one_1bit\one_1bit.cache\ip\2017.4\240847cbae43d9a9\rom1_stub.v 1325 2018-03-28
one_1bit\one_1bit.cache\ip\2017.4\240847cbae43d9a9\rom1_stub.vhdl 1456 2018-03-28
one_1bit\one_1bit.cache\ip\2017.4\240847cbae43d9a9.logs\runme.log 36767 2018-03-28
one_1bit\one_1bit.cache\ip\2017.4\7d303fe8fd36e824\7d303fe8fd36e824.xci 12799 2018-03-28
one_1bit\one_1bit.cache\ip\2017.4\7d303fe8fd36e824\blk_mem_gen_0.dcp 136244 2018-03-28
one_1bit\one_1bit.cache\ip\2017.4\7d303fe8fd36e824\blk_mem_gen_0_sim_netlist.v 202731 2018-03-28
one_1bit\one_1bit.cache\ip\2017.4\7d303fe8fd36e824\blk_mem_gen_0_sim_netlist.vhdl 238234 2018-03-28
one_1bit\one_1bit.cache\ip\2017.4\7d303fe8fd36e824\blk_mem_gen_0_stub.v 1345 2018-03-28
one_1bit\one_1bit.cache\ip\2017.4\7d303fe8fd36e824\blk_mem_gen_0_stub.vhdl 1480 2018-03-28
one_1bit\one_1bit.cache\ip\2017.4\7d303fe8fd36e824.logs\runme.log 37329 2018-03-28
one_1bit\one_1bit.cache\ip\2017.4\f49295174b663700\f49295174b663700.xci 6160 2018-03-28
one_1bit\one_1bit.cache\ip\2017.4\f49295174b663700\mult.dcp 16277 2018-03-28
one_1bit\one_1bit.cache\ip\2017.4\f49295174b663700\mult_sim_netlist.v 17920 2018-03-28
one_1bit\one_1bit.cache\ip\2017.4\f49295174b663700\mult_sim_netlist.vhdl 26382 2018-03-28
one_1bit\one_1bit.cache\ip\2017.4\f49295174b663700\mult_stub.v 1322 2018-03-28
one_1bit\one_1bit.cache\ip\2017.4\f49295174b663700\mult_stub.vhdl 1487 2018-03-28
one_1bit\one_1bit.cache\ip\2017.4\f49295174b663700.logs\runme.log 17565 2018-03-28
one_1bit\one_1bit.cache\wt\gui_handlers.wdf 5272 2018-03-29
one_1bit\one_1bit.cache\wt\java_command_handlers.wdf 1604 2018-03-29
one_1bit\one_1bit.cache\wt\project.wpc 61 2018-03-29
one_1bit\one_1bit.cache\wt\synthesis.wdf 5400 2018-03-28
one_1bit\one_1bit.cache\wt\webtalk_pa.xml 5401 2018-03-29
one_1bit\one_1bit.cache\wt\xsim.wdf 256 2018-03-28
one_1bit\one_1bit.hw\one_1bit.lpr 290 2018-03-28
one_1bit\one_1bit.ip_user_files\ip\blk_mem_gen_0\blk_mem_gen_0.veo 2985 2018-03-28
one_1bit\one_1bit.ip_user_files\ip\blk_mem_gen_0\blk_mem_gen_0.vho 3228 2018-03-28
one_1bit\one_1bit.ip_user_files\ip\blk_mem_gen_0\blk_mem_gen_0_stub.v 1285 2018-03-28
one_1bit\one_1bit.ip_user_files\ip\blk_mem_gen_0\blk_mem_gen_0_stub.vhdl 1364 2018-03-28
one_1bit\one_1bit.ip_user_files\ip\fir_compiler_0\fir_compiler_0.veo 3325 2018-03-28
one_1bit\one_1bit.ip_user_files\ip\fir_compiler_0\fir_compiler_0.vho 3563 2018-03-28
one_1bit\one_1bit.ip_user_files\ip\mult\mult.veo 2972 2018-03-28
one_1bit\one_1bit.ip_user_files\ip\mult\mult.vho 3215 2018-03-28
one_1bit\one_1bit.ip_user_files\ip\mult\mult_stub.v 1244 2018-03-28
one_1bit\one_1bit.ip_user_files\ip\mult\mult_stub.vhdl 1335 2018-03-28
one_1bit\one_1bit.ip_user_files\ip\rom1\rom1.veo 2957 2018-03-28
one_1bit\one_1bit.ip_user_files\ip\rom1\rom1.vho 3191 2018-03-28
one_1bit\one_1bit.ip_user_files\ip\rom1\rom1_stub.v 1247 2018-03-28
one_1bit\one_1bit.ip_user_files\ip\rom1\rom1_stub.vhdl 1304 2018-03-28
one_1bit\one_1bit.ip_user_files\ipstatic\hdl\axi_utils_v2_0_vh_rfs.vhd 292628 2018-03-28
one_1bit\one_1bit.ip_user_files\ipstatic\hdl\fir_compiler_v7_2_vh_rfs.vhd 4294814 2018-03-28
one_1bit\one_1bit.ip_user_files\ipstatic\hdl\mult_gen_v12_0_vh_rfs.vhd 1310888 2018-03-28
one_1bit\one_1bit.ip_user_files\ipstatic\hdl\xbip_bram18k_v3_0_vh_rfs.vhd 103702 2018-03-28
one_1bit\one_1bit.ip_user_files\ipstatic\hdl\xbip_pipe_v3_0_vh_rfs.vhd 30625 2018-03-28
one_1bit\one_1bit.ip_user_files\ipstatic\hdl\xbip_utils_v3_0_vh_rfs.vhd 171224 2018-03-28
one_1bit\one_1bit.ip_user_files\ipstatic\simulation\blk_mem_gen_v8_4.v 171256 2018-03-28
one_1bit\one_1bit.ip_user_files\mem_init_files\blk_mem_gen_0.mif 304095 2018-03-28
one_1bit\one_1bit.ip_user_files\mem_init_files\fir_compiler_0.h 5255 2018-03-28
one_1bit\one_1bit.ip_user_files\mem_init_files\fir_compiler_0.mif 716 2018-03-28
one_1bit\one_1bit.ip_user_files\mem_init_files\PWM.coe 1474536 2018-03-28
one_1bit\one_1bit.ip_user_files\mem_init_files\PWM_phase0.coe 331805 2018-03-28
one_1bit\one_1bit.ip_user_files\mem_init_files\rom1.mif 589788 2018-03-28
one_1bit\one_1bit.ip_user_files\mem_init_files\summary.log 904 2018-03-28
one_1bit\one_1bit.ip_user_files\README.txt 130 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\blk_mem_gen_0.mif 304095 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\blk_mem_gen_0.sh 4911 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\blk_mem_gen_0.udo 0 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\compile.do 686 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\file_info.txt 433 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\glbl.v 1474 2017-12-14
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\PWM_phase0.coe 331805 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\README.txt 2201 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\simulate.do 340 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\summary.log 904 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\wave.do 32 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\ies\blk_mem_gen_0.mif 304095 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\ies\blk_mem_gen_0.sh 5713 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\ies\file_info.txt 433 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\ies\glbl.v 1474 2017-12-14
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\ies\PWM_phase0.coe 331805 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\ies\README.txt 2142 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\ies\run.f 493 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\ies\summary.log 904 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\modelsim\blk_mem_gen_0.mif 304095 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\modelsim\blk_mem_gen_0.sh 5124 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\modelsim\blk_mem_gen_0.udo 0 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\modelsim\compile.do 770 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\modelsim\file_info.txt 433 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\modelsim\glbl.v 1474 2017-12-14
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\modelsim\PWM_phase0.coe 331805 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\modelsim\README.txt 2201 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\modelsim\simulate.do 341 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\modelsim\summary.log 904 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\modelsim\wave.do 32 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\questa\blk_mem_gen_0.mif 304095 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\questa\blk_mem_gen_0.sh 5235 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\questa\blk_mem_gen_0.udo 0 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\questa\compile.do 736 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\questa\elaborate.do 213 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\questa\file_info.txt 433 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\questa\glbl.v 1474 2017-12-14
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\questa\PWM_phase0.coe 331805 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\questa\README.txt 2201 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\questa\simulate.do 203 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\questa\summary.log 904 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\questa\wave.do 32 2018-03-28
one_1bit\one_1bit.ip_user_files\sim_scripts\blk_mem_gen_0\README.txt 3236 2018-03-28

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