利用Verilog实现数字秒表（基本逻辑设计分频器练习）
设置复位开关。当按下复位开关时，秒表清零并做好计时准备。在任何情况下只要按下复位开关，秒表都要无条件地进行复位操作，即使是在计时过程中也要无条件地进行清零操作。
设置启/停开关。当按下启/停开关后，将启动秒表输出，当再按一下启/停开关时，将终止秒表的输出。
采用结构化设计风格描述，即先设计一个10分频电路，再用此电路构建秒表电路。(Using Verilog to realize digital stopwatch (basic logic design frequency divider practice)
Set the reset switch. When the reset switch is pressed, the stopwatch is zero and the timing is ready. In any case, as long as we press the reset switch, the stopwatch is unconditionally reset operation, even in the process of timing, we must do zero clearing operation without any conditions.
Set up / stop switch. When the start / stop switch is pressed, the stopwatch output will be started. When the start / stop switch is pressed, the stopwatch output will be terminated.
The structure design style is described, that is, first design a 10 frequency division circuit, then use this circuit to build a stopwatch circuit.)